[coreboot-gerrit] New patch to review for coreboot: soc/intel/fsp_baytrail: Adjust root port INT routing

[Martin Roth (martinroth@google.com)]

Martin Roth (martinroth at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12684

-gerrit

commit 3bfced94ab3621c90a417199fdeb18d3ff00e336
Author: Martin Roth <martinroth at google.com>
Date:   Mon Dec 7 16:50:47 2015 -0700

    soc/intel/fsp_baytrail: Adjust root port INT routing
    
    Adjust the root port INT routing based on Bay Trail spec:
    Document Number: 538136, Rev. 3.9
    
    Table 241. Interrupt Generated for INT[A-D] Interrupts
                 INTA  INTB  INTC  INTD
    Root Port 1 INTA# INTB# INTC# INTD#
    Root Port 2 INTD# INTA# INTB# INTC#
    Root Port 3 INTC# INTD# INTA# INTB#
    Root Port 4 INTB# INTC# INTD# INTA#
    
    Change-Id: I22a8c0bc6ad731dfb79385d6e165f1ec0a07507d
    Signed-off-by: Martin Roth <martinroth at google.com>
---
 src/soc/intel/fsp_baytrail/southcluster.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 6182948..a49f6d7 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -208,6 +208,15 @@ static void write_pci_config_irqs(void)
 		if (targ_dev == NULL || new_int_pin < 1)
 			continue;
 
+		/*
+		 * Adjust the INT routing for the PCIe root ports
+		 * See 'Interrupt Generated for INT[A-D] Interrupts'
+		 * Table 241 in Document Number: 538136, Rev. 3.9
+		 */
+		if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV)
+			new_int_pin = (new_int_pin +
+				       PCI_FUNC(targ_dev->path.pci.devfn)) % 4;
+
 		/* Get the original INT_PIN for record keeping */
 		original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);