[coreboot-gerrit] New patch to review for coreboot: a6d92cb AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration [NOTFORMERGE]

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8389

-gerrit

commit a6d92cb224a8f7b47f9b183ebc757baa71ddffa7
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Feb 7 12:27:27 2015 +0200

    AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration [NOTFORMERGE]
    
    Now that PCI subsystem properly configures PCI bridges that are
    marked disabled, fix devicetree entries for the boards that do not
    implement PCI slots or integrated PCI devices.
    
    Change-Id: Icef85af051567a3da0ec429469fb3ecaccb83a48
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/mainboard/asrock/e350m1/devicetree.cb     | 2 +-
 src/mainboard/gizmosphere/gizmo/devicetree.cb | 2 +-
 src/mainboard/pcengines/apu1/devicetree.cb    | 2 +-
 src/southbridge/amd/cimx/sb800/late.c         | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb
index 0690664..7f44869 100644
--- a/src/mainboard/asrock/e350m1/devicetree.cb
+++ b/src/mainboard/asrock/e350m1/devicetree.cb
@@ -94,7 +94,7 @@ chip northbridge/amd/agesa/family14/root_complex
 							device pnp 2e.f off end #  GPIO_PP_OD
 						end
 					end #LPC
-					device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
+					device pci 14.4 off end # PCIB 0x4384
 					device pci 14.5 on end # USB 2
 					device pci 15.0 on  end # PCIe PortA
 					device pci 15.1 on  end # PCIe PortB: NIC
diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb
index 8cd4cd3..baa10b3 100644
--- a/src/mainboard/gizmosphere/gizmo/devicetree.cb
+++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb
@@ -48,7 +48,7 @@ chip northbridge/amd/agesa/family14/root_complex
 				device pci 14.1 on end # IDE	0x439c
 				device pci 14.2 on end # HDA	0x4383
 				device pci 14.3 on end # LPC	0x439d
-				device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed
+				device pci 14.4 off end # PCIB 0x4384
 				device pci 14.5 off end # USB 2
 				device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector
 				device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 4209ba6..3c0b795 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -74,7 +74,7 @@ chip northbridge/amd/agesa/family14/root_complex
 						device pnp 2e.e off end
 					end
 					end #LPC
-					device pci 14.4 on end # PCIB 0x4384
+					device pci 14.4 off end # PCIB 0x4384
 					device pci 14.5 off end # OHCI FS/LS USB
 					#device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699)
 					device pci 15.0 on end # PCIe PortA
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index ccb33b9..510bf23 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -400,7 +400,7 @@ static void sb800_enable(device_t dev)
 		 * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
 		 *              to function as GPIO {GPIO 35:0}.
 		 */
-		if (!IS_ENABLED(CONFIG_BOARD_PCENGINES_APU1) && dev->enabled)
+		if (dev->enabled)
 			RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
 		else
 			RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0);