[coreboot-gerrit] New patch to review for coreboot: bootstate: remove need for #ifdef ENV_RAMSTAGE
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Sep 2 22:37:45 CET 2015
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11492
-gerrit
commit 4195c04a02d1811294256acdabc74b55b15bf2f3
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Sep 2 17:34:04 2015 -0500
bootstate: remove need for #ifdef ENV_RAMSTAGE
The BOOT_STATE_INIT_ENTRY macro can only be used in ramstage, however
the current state of the header meant bad build errors in non-ramstage.
Therefore, people had to #ifdef in the source. Remove that requirement.
Change-Id: I8755fc68bbaca6b72fbe8b4db4bcc1ccb35622bd
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/drivers/intel/fsp1_0/fsp_util.c | 3 ---
src/drivers/intel/fsp1_1/fsp_util.c | 4 ----
src/include/bootstate.h | 8 +++++---
src/lib/cbmem_common.c | 5 ++++-
src/northbridge/intel/haswell/mrccache.c | 3 +--
src/northbridge/intel/sandybridge/mrccache.c | 3 +--
src/soc/intel/baytrail/spi.c | 2 --
src/soc/intel/braswell/spi.c | 4 ----
src/soc/intel/broadwell/spi.c | 2 --
src/soc/intel/common/mrc_cache.c | 19 ++-----------------
src/southbridge/intel/common/spi.c | 3 +--
11 files changed, 14 insertions(+), 42 deletions(-)
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index 9dbd502..f1e0d11 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -215,8 +215,6 @@ void * find_fsp_reserved_mem(void *hob_list_ptr)
}
#endif /* FSP_RESERVE_MEMORY_SIZE */
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */
-
void print_fsp_info(void) {
if (fsp_header_ptr == NULL)
@@ -349,4 +347,3 @@ BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, fsp_finalize, NULL);
/* Update the MRC/fast boot cache as part of the late table writing stage */
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY,
find_fsp_hob_update_mrc, NULL);
-#endif /* #ifndef __PRE_RAM__ */
diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c
index 18e8648..bce4337 100644
--- a/src/drivers/intel/fsp1_1/fsp_util.c
+++ b/src/drivers/intel/fsp1_1/fsp_util.c
@@ -134,8 +134,6 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
#endif
}
-#if ENV_RAMSTAGE
-
void fsp_notify(u32 phase)
{
FSP_NOTIFY_PHASE notify_phase_proc;
@@ -189,8 +187,6 @@ BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
fsp_notify_boot_state_callback,
(void *)EnumInitPhaseReadyToBoot);
-#endif /* ENV_RAMSTAGE */
-
struct fsp_runtime {
uint32_t fih;
uint32_t hob_list;
diff --git a/src/include/bootstate.h b/src/include/bootstate.h
index 4952780..1bbe458 100644
--- a/src/include/bootstate.h
+++ b/src/include/bootstate.h
@@ -19,8 +19,7 @@
#ifndef BOOTSTATE_H
#define BOOTSTATE_H
-#if !defined(__SMM__) && !defined(__PRE_RAM__)
-
+#include <rules.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>
@@ -185,7 +184,11 @@ struct boot_state_init_entry {
struct boot_state_callback bscb;
};
+#if ENV_RAMSTAGE
#define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init")))
+#else
+#define BOOT_STATE_INIT_ATTR __attribute__ ((unused))
+#endif
#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \
static struct boot_state_init_entry func_ ##_## state_ ##_## when_ = \
@@ -198,5 +201,4 @@ struct boot_state_init_entry {
bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \
& func_ ##_## state_ ##_## when_;
-#endif
#endif /* BOOTSTATE_H */
diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c
index d3019c5..143935e 100644
--- a/src/lib/cbmem_common.c
+++ b/src/lib/cbmem_common.c
@@ -43,9 +43,12 @@ void __attribute__((weak)) cbmem_fail_resume(void)
{
}
-#if ENV_RAMSTAGE && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
+#if !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
static void init_cbmem_post_device(void *unused)
{
+ if (IS_ENABLED(CONFIG_EARLY_CBMEM_INIT))
+ return;
+
if (acpi_is_wakeup())
cbmem_initialize();
else
diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c
index eb603f6..bbc5e51 100644
--- a/src/northbridge/intel/haswell/mrccache.c
+++ b/src/northbridge/intel/haswell/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
/* SPI code needs malloc/free.
* Also unknown if writing flash from XIP-flash code is a good idea
*/
-#if !defined(__PRE_RAM__)
+
/* find the first empty block in the MRC cache area.
* If there's none, return NULL.
*
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
struct mrc_data_container *find_current_mrc_cache(void)
{
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index f89fc0f..2086427 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -128,7 +128,7 @@ static struct mrc_data_container *find_current_mrc_cache_local
/* SPI code needs malloc/free.
* Also unknown if writing flash from XIP-flash code is a good idea
*/
-#if !defined(__PRE_RAM__)
+
/* find the first empty block in the MRC cache area.
* If there's none, return NULL.
*
@@ -229,7 +229,6 @@ static void update_mrc_cache(void *unused)
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-#endif
struct mrc_data_container *find_current_mrc_cache(void)
{
diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c
index b1fc692..380b23f 100644
--- a/src/soc/intel/baytrail/spi.c
+++ b/src/soc/intel/baytrail/spi.c
@@ -316,14 +316,12 @@ void spi_init(void)
ich_set_bbar(0);
}
-#ifndef __SMM__
static void spi_init_cb(void *unused)
{
spi_init();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
int spi_claim_bus(struct spi_slave *slave)
{
diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c
index afc288a..453a719 100644
--- a/src/soc/intel/braswell/spi.c
+++ b/src/soc/intel/braswell/spi.c
@@ -295,8 +295,6 @@ void spi_init(void)
cntlr.preop = &ich9_spi->preop;
}
-#if ENV_RAMSTAGE
-
static void spi_init_cb(void *unused)
{
spi_init();
@@ -304,8 +302,6 @@ static void spi_init_cb(void *unused)
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif /* ENV_RAMSTAGE */
-
int spi_claim_bus(struct spi_slave *slave)
{
/* Handled by ICH automatically. */
diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c
index a75ee83..c159e20 100644
--- a/src/soc/intel/broadwell/spi.c
+++ b/src/soc/intel/broadwell/spi.c
@@ -312,14 +312,12 @@ void spi_init(void)
pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
}
-#if ENV_RAMSTAGE
static void spi_init_cb(void *unused)
{
spi_init();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
int spi_claim_bus(struct spi_slave *slave)
{
diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c
index 9a066d5..e5e6b6a 100644
--- a/src/soc/intel/common/mrc_cache.c
+++ b/src/soc/intel/common/mrc_cache.c
@@ -18,11 +18,13 @@
*/
#include <string.h>
+#include <bootstate.h>
#include <console/console.h>
#include <cbmem.h>
#include <fmap.h>
#include <ip_checksum.h>
#include "mrc_cache.h"
+#include "nvm.h"
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
@@ -154,12 +156,6 @@ int mrc_cache_get_current(const struct mrc_saved_data **cache)
return __mrc_cache_get_current(®ion, cache);
}
-#if ENV_ROMSTAGE
-
-/*
- * romstage code
- */
-
/* Fill in mrc_saved_data structure with payload. */
static void mrc_cache_fill(struct mrc_saved_data *cache, void *data,
size_t size)
@@ -197,15 +193,6 @@ int mrc_cache_stash_data(void *data, size_t size)
return 0;
}
-#else
-
-/*
- * ramstage code
- */
-
-#include <bootstate.h>
-#include "nvm.h"
-
static int mrc_slot_valid(const struct mrc_data_region *region,
const struct mrc_saved_data *slot,
const struct mrc_saved_data *to_save)
@@ -330,5 +317,3 @@ static void update_mrc_cache(void *unused)
}
BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL);
-
-#endif /* ENV_ROMSTAGE */
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 1d3ebf6..5d18012 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -359,14 +359,13 @@ void spi_init(void)
bios_cntl &= ~(1 << 5);
pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1);
}
-#ifndef __SMM__
+
static void spi_init_cb(void *unused)
{
spi_init();
}
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
-#endif
int spi_claim_bus(struct spi_slave *slave)
{
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