[coreboot-gerrit] New patch to review for coreboot: glados: Fix incorrect comment format in devicetree.cb

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11553

-gerrit

commit d9aceefb964ddef553e5d28ad1155ab575db4c66
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 09:49:08 2015 -0700

    glados: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the glados
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-glados coreboot
    
    Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
    Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296301
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/glados/devicetree.cb | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 2c6d997..40fe2b1 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -20,17 +20,17 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
-	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
-	register "PortUsb20Enable[4]" = "1"	/* Type-A Port 1 */
-	register "PortUsb20Enable[6]" = "1"	/* Camera */
-	register "PortUsb20Enable[8]" = "1"	/* Type-A Port 2 */
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port 1
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port 2
 
-	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb30Enable[2]" = "1"	/* Type-A Port 1 */
-	register "PortUsb30Enable[3]" = "1"	/* Type-A Port 2 */
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port 1
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port 2
 
 	# Enable Root port 1 and 5.
 	register "PcieRpEnable[0]" = "1"