[coreboot-gerrit] New patch to review for coreboot: kunimitsu: Fix incorrect comment format in devicetree.cb

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11554

-gerrit

commit ed2211e7ff053cc105151c6643ece24d91a3e074
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Aug 31 10:01:03 2015 -0700

    kunimitsu: Fix incorrect comment format in devicetree.cb
    
    The devicetree.cb compiler can't handle C style /**/ comments,
    they need to be shell-style #.  Due to a last minute formatting
    change in my commit to enable USB ports this broke the kunimitsu
    build.
    
    BUG=chrome-os-partner:44662
    BRANCH=none
    TEST=emerge-kunimitsu coreboot
    
    Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
    Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
    Original-Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/296302
    Original-Tested-by: Wenkai Du <wenkai.du at intel.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/intel/kunimitsu/devicetree.cb | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index 1c3cf67..5cc4f2e 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,17 +15,17 @@ chip soc/intel/skylake
 		[PchSerialIoIndexUart2] = PchSerialIoPci, \
 	}"
 
-	register "PortUsb20Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb20Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb20Enable[2]" = "1"	/* Bluetooth */
-	register "PortUsb20Enable[4]" = "1"	/* Type-A Port (card) */
-	register "PortUsb20Enable[6]" = "1"	/* Camera */
-	register "PortUsb20Enable[8]" = "1"	/* Type-A Port (board) */
-
-	register "PortUsb30Enable[0]" = "1"	/* Type-C Port 1 */
-	register "PortUsb30Enable[1]" = "1"	/* Type-C Port 2 */
-	register "PortUsb30Enable[2]" = "1"	/* Type-A Port (card) */
-	register "PortUsb30Enable[3]" = "1"	/* Type-A Port (board) */
+	register "PortUsb20Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb20Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb20Enable[2]" = "1"	# Bluetooth
+	register "PortUsb20Enable[4]" = "1"	# Type-A Port (card)
+	register "PortUsb20Enable[6]" = "1"	# Camera
+	register "PortUsb20Enable[8]" = "1"	# Type-A Port (board)
+
+	register "PortUsb30Enable[0]" = "1"	# Type-C Port 1
+	register "PortUsb30Enable[1]" = "1"	# Type-C Port 2
+	register "PortUsb30Enable[2]" = "1"	# Type-A Port (card)
+	register "PortUsb30Enable[3]" = "1"	# Type-A Port (board)
 
 	register "pirqa_routing" = "0x8b"
 	register "pirqb_routing" = "0x8a"