[coreboot-gerrit] New patch to review for coreboot: google/lars: Set I2C[4] port voltage to 1.8v

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13627

-gerrit

commit 41e23bd3791845ab4d2ab6551c168cff356773c8
Author: david <david_wu at quantatw.com>
Date:   Fri Jan 8 20:49:48 2016 +0800

    google/lars: Set I2C[4] port voltage to 1.8v
    
    As the audio card needs 1.8V I2C operation. This patch adds
    entry into devicetree.cb to set I2C port 4 operate at 1.8V.
    
    TEST=Built & booted lars board. Verified that I2C
    port 4 is operating at 1.8V level
    
    Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
    Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/321000
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/mainboard/google/lars/devicetree.cb | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index bc39f3e..cf3649a 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -146,6 +146,7 @@ chip soc/intel/skylake
 	register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # SD
 	register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+	register "SerialIoI2cVoltage[4]" = "1"         # I2C4 is 1.8V
 
 	# Must leave UART0 enabled or SD/eMMC will not work as PCI
 	register "SerialIoDevMode" = "{ \