[coreboot-gerrit] New patch to review for coreboot: intel/skylake: Add gpio macro for unused GPIO pins

[Patrick Georgi (pgeorgi@google.com)]

Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13628

-gerrit

commit da6a69ca48e090c05ab92f55c25679d34da06493
Author: david <david_wu at quantatw.com>
Date:   Tue Dec 29 15:02:04 2015 +0800

    intel/skylake: Add gpio macro for unused GPIO pins
    
    Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
    GPIO TX/RX will be disabled.
    
    BUG=none
    BRANCH=none
    TEST=Build and boot lars
    
    Change-Id: I3a6fcd2f3462e8e0d1273aa80b1599b76b160825
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: 889bfd66dbc918e9fb0ba1b95b63fd7a3bf180d9
    Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
    Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/319964
    Original-Commit-Ready: David Wu <david_wu at quantatw.com>
    Original-Tested-by: David Wu <david_wu at quantatw.com>
    Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj at intel.com>
    Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati at intel.com>
---
 src/soc/intel/skylake/include/soc/gpio.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index 7dec874..f2246e9 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -108,6 +108,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
 	_PAD_CFG(pad_, term_, \
 	_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO))
 
+/* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and
+   GPIO TX/RX will be disabled. */
+#define PAD_CFG_NC(pad_) \
+	_PAD_CFG(pad_, NONE, \
+	_DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES))
+
 /* General purpose output with termination. */
 #define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \
 	_PAD_CFG(pad_, term_, \