[coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1: Supply TPM modules on the LPC connector

[Tobias Diedrich (ranma+coreboot@tdiedrich.de)]

Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796

-gerrit

commit 08c2ac39424e565a63efa60256c8c4f4ffa63299
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date:   Wed Dec 23 23:27:06 2015 +0100

    pcengines/apu1: Supply TPM modules on the LPC connector
    
    Since the APU1 has an LPC connector it is possible to
    connect a TPM. I'm using mine mostly for the HWRNG which the
    APU1 lacks.
    
    This takes care of setting up the TPM interrupt.
    Interrupt 5 was chosen since it is not otherwise used on the APU1,
    Alternatively 1, 7, 10-11 and 14-15 should be available as well.
    It may also be possible to share the ACPI interrupt (9).
    
    Previously I was getting frequent
    "genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)"
    errors.
    
    With this I also no longer need to use "tpm_tis.force=1" on
    the kernel commandline since the TPM is now declared in the
    ACPI DSDT.
    
    The tpm support asl is changed to probe for the TPM before returning
    "Device present" status, so it will fail gracefully if no TPM module
    is installed.
    
    See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa
    and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
    
    Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd
    Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
 src/drivers/pc80/tpm/acpi/tpm.asl           | 39 ++++++++++++++++++-----------
 src/mainboard/pcengines/apu1/Kconfig        |  1 +
 src/mainboard/pcengines/apu1/devicetree.cb  |  5 ++++
 src/southbridge/amd/cimx/sb800/acpi/lpc.asl |  4 +++
 4 files changed, 34 insertions(+), 15 deletions(-)

diff --git a/src/drivers/pc80/tpm/acpi/tpm.asl b/src/drivers/pc80/tpm/acpi/tpm.asl
index 7755e9b..de25114 100644
--- a/src/drivers/pc80/tpm/acpi/tpm.asl
+++ b/src/drivers/pc80/tpm/acpi/tpm.asl
@@ -21,10 +21,33 @@ Device (TPM)
 	Name (_CID, 0x310cd041)
 	Name (_UID, 1)
 
+	OperationRegion (TREG, SystemMemory,
+			 CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)
+	Field (TREG, ByteAcc, NoLock, Preserve)
+	{
+		/* TPM_INT_ENABLE_0 */
+		Offset (0x0008),
+		, 3,
+		ITPL, 2,  /* Interrupt type and polarity */
+
+		/* TPM_INT_VECTOR_0 */
+		Offset (0x000C),
+		IVEC, 4,  /* SERIRQ vector */
+
+		/* TPM_DID_VID */
+		Offset (0x0f00),
+		DVID, 32,  /* Device and vendor ID */
+	}
+
 	Method (_STA, 0)
 	{
 #if CONFIG_LPC_TPM && !CONFIG_TPM_DEACTIVATE
-		Return (0xf)
+		If (LAnd (LGreater (DVID, 0), LLess (DVID, 0xffffffff))) {
+			Return (0xf)
+		} Else {
+			/* TPM module missing */
+			Return (0x0)
+		}
 #else
 		Return (0x0)
 #endif
@@ -45,20 +68,6 @@ Device (TPM)
 
 	Method (_CRS, 0, Serialized)
 	{
-		OperationRegion (TREG, SystemMemory,
-				 CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000)
-		Field (TREG, ByteAcc, NoLock, Preserve)
-		{
-			/* TPM_INT_ENABLE_0 */
-			Offset (0x0008),
-			, 3,
-			ITPL, 2,  /* Interrupt type and polarity */
-
-			/* TPM_INT_VECTOR_0 */
-			Offset (0x000C),
-			IVEC, 4,  /* SERIRQ vector */
-		}
-
 		CreateField (^IBUF, ^TIRQ._INT, 32, TVEC)
 		CreateBitField (^IBUF, ^TIRQ._HE, TTYP)
 		CreateBitField (^IBUF, ^TIRQ._LL, TPOL)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 2328776..5eb9e1c 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select HAVE_CMOS_DEFAULT
 	select BOARD_ROMSIZE_KB_2048
 	select SPD_CACHE
+	select MAINBOARD_HAS_LPC_TPM
 
 config MAINBOARD_DIR
 	string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..1a263a2 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex
 					device pci 14.1 off end # IDE	0x439c
 					device pci 14.2 off end # HDA	0x4383
 					device pci 14.3 on # LPC		0x439d
+					chip drivers/pc80/tpm # Support TPM on the LPC header.
+						device pnp 0c31.0 on
+							irq 0x70 = 5
+						end
+					end
 					chip superio/nuvoton/nct5104d
 						register "irq_trigger_type" = "0"
 						device pnp 2e.0 off end
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
index 98d5aa5..c2d1ebd 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
@@ -77,4 +77,8 @@ Device(LIBR) {
 		})
 	} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
 	#include "acpi/superio.asl"
+
+#if CONFIG_MAINBOARD_HAS_LPC_TPM
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+#endif
 } /* end LIBR */