[coreboot-gerrit] Patch set updated for coreboot: pcengines/apu1: Supply TPM modules on the LPC connector
Tobias Diedrich (ranma+coreboot@tdiedrich.de)
gerrit at coreboot.org
Thu Feb 25 08:36:35 CET 2016
Tobias Diedrich (ranma+coreboot at tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796
-gerrit
commit 8de6e3167b70f6c84b54dc9c1b81d33235fc92cf
Author: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
Date: Wed Dec 23 23:27:06 2015 +0100
pcengines/apu1: Supply TPM modules on the LPC connector
Since the APU1 has an LPC connector it is possible to
connect a TPM. I'm using mine mostly for the HWRNG which the
APU1 lacks.
This takes care of setting up the TPM interrupt.
Interrupt 5 was chosen since it is not otherwise used on the APU1,
Alternatively 1, 7, 10-11 and 14-15 should be available as well.
It may also be possible to share the ACPI interrupt (9).
Previously I was getting frequent
"genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)"
errors.
With this I also no longer need to use "tpm_tis.force=1" on
the kernel commandline since the TPM is now declared in the
ACPI DSDT.
See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa
and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd
Signed-off-by: Tobias Diedrich <ranma+coreboot at tdiedrich.de>
---
src/mainboard/pcengines/apu1/Kconfig | 1 +
src/mainboard/pcengines/apu1/devicetree.cb | 5 +++++
src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 4 ++++
3 files changed, 10 insertions(+)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 2328776..5eb9e1c 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
select SPD_CACHE
+ select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..1a263a2 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
+ chip drivers/pc80/tpm # Support TPM on the LPC header.
+ device pnp 0c31.0 on
+ irq 0x70 = 5
+ end
+ end
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
index 98d5aa5..c2d1ebd 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
@@ -77,4 +77,8 @@ Device(LIBR) {
})
} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
#include "acpi/superio.asl"
+
+#if CONFIG_MAINBOARD_HAS_LPC_TPM
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+#endif
} /* end LIBR */
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