[coreboot-gerrit] Patch set updated for coreboot: WIP: mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
Denis Carikli (GNUtoo@no-log.org)
gerrit at coreboot.org
Tue Feb 23 01:51:15 CET 2016
Denis Carikli (GNUtoo at no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12301
-gerrit
commit 22f91ddb542f7693d30c10279f0fe0b848939bfd
Author: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
Date: Sun Jul 26 19:57:51 2015 +0200
WIP: mainboard/asus: Add F2A85-M PRO variant to F2A85-M.
The board boots.
-> The GPU works.
-> USB keyboard and mouse work.
-> Not all USB ports were fully tested.
-> The onboard ethernet card doesn't work.
-> Serial doesn't work: Linux, GRUB and userspace
sees it, but a remote computer doesn't see any
output.
Change-Id: I78389dc1fd19a2354daec0484042940cf8b490ae
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo at no-log.org>
---
src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c | 1 +
src/mainboard/asus/f2a85-m_pro/Kconfig | 93 +++++++++++++
src/mainboard/asus/f2a85-m_pro/Kconfig.name | 2 +
src/mainboard/asus/f2a85-m_pro/Makefile.inc | 26 ++++
src/mainboard/asus/f2a85-m_pro/OptionsIds.h | 1 +
src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c | 1 +
.../asus/f2a85-m_pro/PlatformGnbPcieComplex.h | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/routing.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/sata.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/si.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/superio.asl | 16 +++
src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl | 1 +
src/mainboard/asus/f2a85-m_pro/acpi_tables.c | 1 +
src/mainboard/asus/f2a85-m_pro/board_info.txt | 7 +
src/mainboard/asus/f2a85-m_pro/buildOpts.c | 1 +
src/mainboard/asus/f2a85-m_pro/cmos.layout | 79 +++++++++++
src/mainboard/asus/f2a85-m_pro/devicetree.cb | 146 +++++++++++++++++++++
src/mainboard/asus/f2a85-m_pro/dsdt.asl | 1 +
src/mainboard/asus/f2a85-m_pro/irq_tables.c | 1 +
src/mainboard/asus/f2a85-m_pro/mainboard.c | 1 +
src/mainboard/asus/f2a85-m_pro/mptable.c | 1 +
src/mainboard/asus/f2a85-m_pro/romstage.c | 134 +++++++++++++++++++
28 files changed, 523 insertions(+)
diff --git a/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c
new file mode 100644
index 0000000..afa69bb
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/BiosCallOuts.c
@@ -0,0 +1 @@
+#include "../f2a85-m/BiosCallOuts.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig b/src/mainboard/asus/f2a85-m_pro/Kconfig
new file mode 100644
index 0000000..4353444
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Kconfig
@@ -0,0 +1,93 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+# Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+if BOARD_ASUS_F2A85_M_PRO
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select CPU_AMD_AGESA_FAMILY15_TN
+ select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN
+ select SOUTHBRIDGE_AMD_AGESA_HUDSON
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select SUPERIO_NUVOTON_NCT6779D
+ select BOARD_ROMSIZE_KB_8192
+ select GFXUMA
+ select HUDSON_DISABLE_IMC
+
+choice
+ prompt "DDR3 memory voltage"
+ default BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135
+ bool "1.35V"
+ help
+ Set DRR3 memory voltage to 1.35V
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+ bool "1.50V"
+ help
+ Set DRR3 memory voltage to 1.50V
+config BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165
+ bool "1.65V"
+ help
+ Set DRR3 memory voltage to 1.65V
+endchoice
+
+config BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL
+ hex
+ default 0x9e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_135
+ default 0x0 if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_150
+ default 0x1e if BOARD_ASUS_F2A85_M_PRO_DDR3_VOLT_165
+
+config MAINBOARD_DIR
+ string
+ default asus/f2a85-m_pro
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "F2A85-M_PRO"
+
+config HW_MEM_HOLE_SIZEK
+ hex
+ default 0x200000
+
+config MAX_CPUS
+ int
+ default 4
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+ bool
+ default n
+
+config IRQ_SLOT_COUNT
+ int
+ default 11
+
+config ONBOARD_VGA_IS_PRIMARY
+ bool
+ default y
+
+config VGA_BIOS_ID
+ string
+ default "1002,9993"
+
+endif # BOARD_ASUS_F2A85_M_PRO
diff --git a/src/mainboard/asus/f2a85-m_pro/Kconfig.name b/src/mainboard/asus/f2a85-m_pro/Kconfig.name
new file mode 100644
index 0000000..e4b8dfd
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASUS_F2A85_M_PRO
+ bool "F2A85-M PRO"
diff --git a/src/mainboard/asus/f2a85-m_pro/Makefile.inc b/src/mainboard/asus/f2a85-m_pro/Makefile.inc
new file mode 100644
index 0000000..0008d6d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/Makefile.inc
@@ -0,0 +1,26 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+romstage-y += buildOpts.c
+romstage-y += BiosCallOuts.c
+romstage-y += PlatformGnbPcie.c
+
+ramstage-y += buildOpts.c
+ramstage-y += BiosCallOuts.c
+ramstage-y += PlatformGnbPcie.c
diff --git a/src/mainboard/asus/f2a85-m_pro/OptionsIds.h b/src/mainboard/asus/f2a85-m_pro/OptionsIds.h
new file mode 100644
index 0000000..c702a9c
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/OptionsIds.h
@@ -0,0 +1 @@
+#include "../f2a85-m/OptionsIds.h"
diff --git a/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c
new file mode 100644
index 0000000..d83a779
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcie.c
@@ -0,0 +1 @@
+#include "../f2a85-m/PlatformGnbPcie.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h
new file mode 100644
index 0000000..f6f4c9a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/PlatformGnbPcieComplex.h
@@ -0,0 +1 @@
+#include "../f2a85-m/PlatformGnbPcieComplex.h"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl
new file mode 100644
index 0000000..43c2428
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/AmdImc.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/AmdImc.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl
new file mode 100644
index 0000000..29c8d69
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/cpstate.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/cpstate.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl
new file mode 100644
index 0000000..4794311
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/gpe.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/gpe.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl
new file mode 100644
index 0000000..f81742e
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/mainboard.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/mainboard.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl
new file mode 100644
index 0000000..77a1f8a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/routing.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/routing.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl
new file mode 100644
index 0000000..46bc2e6
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/sata.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/sata.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/si.asl b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl
new file mode 100644
index 0000000..208e5c4
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/si.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/si.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl
new file mode 100644
index 0000000..67e4e2b
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/sleep.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/sleep.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl
new file mode 100644
index 0000000..6f95a8a
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/superio.asl
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* No Super I/O device or functionality yet */
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl
new file mode 100644
index 0000000..3d529e5
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/thermal.asl
@@ -0,0 +1 @@
+#include "../../f2a85-m/acpi/thermal.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl
new file mode 100644
index 0000000..1b3fba0
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi/usb_oc.asl
@@ -0,0 +1 @@
+include "../../f2a85-m/acpi/usb_oc.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/acpi_tables.c b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c
new file mode 100644
index 0000000..febb723
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/acpi_tables.c
@@ -0,0 +1 @@
+#include "../f2a85-m/acpi_tables.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/board_info.txt b/src/mainboard/asus/f2a85-m_pro/board_info.txt
new file mode 100644
index 0000000..52c5819
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: http://www.asus.com/Motherboards/F2A85M_PRO/
+ROM package: DIP8
+ROM protocol: SPI
+ROM socketed: y
+Flashrom support: y
+Release year:
diff --git a/src/mainboard/asus/f2a85-m_pro/buildOpts.c b/src/mainboard/asus/f2a85-m_pro/buildOpts.c
new file mode 100644
index 0000000..c9fc086
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/buildOpts.c
@@ -0,0 +1 @@
+#include "../f2a85-m/buildOpts.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/cmos.layout b/src/mainboard/asus/f2a85-m_pro/cmos.layout
new file mode 100644
index 0000000..50750a8
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/cmos.layout
@@ -0,0 +1,79 @@
+#*****************************************************************************
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#*****************************************************************************
+
+entries
+
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 multi_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+456 1 e 1 ECC_memory
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 amd_reserved
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/asus/f2a85-m_pro/devicetree.cb b/src/mainboard/asus/f2a85-m_pro/devicetree.cb
new file mode 100644
index 0000000..34a57a9
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/devicetree.cb
@@ -0,0 +1,146 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2012 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+chip northbridge/amd/agesa/family15tn/root_complex
+
+ device cpu_cluster 0 on
+ chip cpu/amd/agesa/family15tn
+ device lapic 10 on end
+ end
+ end
+
+ device domain 0 on
+ subsystemid 0x1022 0x1410 inherit
+ chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+
+ chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+ device pci 0.0 on end # Root Complex
+ device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
+ device pci 1.1 on end # Internal Multimedia
+ device pci 2.0 on end # PCIE SLOT0 x16 blue
+ device pci 3.0 on end # unused?
+ device pci 4.0 on end # PCIE 4x black
+ device pci 5.0 on end # unused?
+ device pci 6.0 on end # unused?
+ device pci 7.0 on end # LAN
+ device pci 8.0 on end # NB/SB Link P2P bridge
+ end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex
+
+ chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus
+ device pci 10.0 on end # XHCI HC0
+ device pci 10.1 on end # XHCI HC1
+ device pci 11.0 on end # SATA
+ device pci 12.0 on end # USB
+ device pci 12.2 on end # USB
+ device pci 13.0 on end # USB
+ device pci 13.2 on end # USB
+ device pci 14.0 on # SMBUS
+ chip drivers/generic/generic #dimm 0
+ device i2c 50 on end # 7-bit SPD address
+ end
+ chip drivers/generic/generic #dimm 1
+ device i2c 51 on end # 7-bit SPD address
+ end
+ end # SM
+ device pci 14.1 on end # IDE 0x439c
+ device pci 14.2 on end # HDA 0x4383
+ device pci 14.3 on # LPC 0x439d
+ chip superio/nuvoton/nct5572d
+ device pnp 2e.0 off end # FDC
+ device pnp 2e.1 off end # LPT1
+ device pnp 2e.2 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off end # COM2/IR
+ device pnp 2e.5 off end # Keyboard
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 on # GPIO6, GPIO7, GPIO8
+ io 0xe0 = 0x7f
+ io 0xe1 = 0x10
+ io 0xe5 = 0xff
+ io 0xe6 = 0xff
+ io 0xe7 = 0xff
+ io 0xed = 0xff
+ io 0xf5 = 0xff
+ end
+ device pnp 2e.8 on # WDT1, GPIO0, GPIO1
+ io 0x30 = 0x02
+ io 0xe1 = 0x80
+ io 0xf1 = 0x28
+ io 0xf4 = 0x08
+ io 0xf5 = 0xff
+ io 0xf7 = 0xff
+ end
+ device pnp 2e.9 on # GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8
+ io 0x30 = 0xfe
+ io 0xe1 = 0x90
+ io 0xe5 = 0x76
+ io 0xf1 = 0x7b
+ io 0xf5 = 0xff
+ end
+ device pnp 2e.a on # ACPI
+ io 0xe6 = 0x5c
+ io 0xe7 = 0x11
+ io 0xf2 = 0x5d
+ end
+ device pnp 2e.b on # Hardware Monitor, Front Panel LED
+ io 0x30 = 0x01
+ io 0x60 = 0x02
+ io 0x61 = 0x90
+ io 0xe2 = 0x7f
+ io 0xe4 = 0xf1
+ end
+ device pnp 2e.d off end # WDT1
+ device pnp 2e.e off end # CIR WAKE-UP
+ device pnp 2e.f off # GPIO Push-pull/Open-drain selection
+ io 0xe6 = 7f
+ end
+ device pnp 2e.14 off # PORT80 UART
+ io 0xe0 = 0x00
+ end
+ device pnp 2e.16 off end # Deep Sleep
+ end
+ end #device pci 14.3 # LPC
+ device pci 14.4 on end # PCI 0x4384
+ device pci 14.5 on end # USB 2
+ device pci 14.6 on end # Gec
+ device pci 14.7 on end # SD
+ device pci 15.0 on end # PCIe 0 - onboard PCIe 1x
+ device pci 15.1 on end # PCIe 1 onboard gigabit
+ device pci 15.2 on end # unused
+ device pci 15.3 on end # unused
+
+ end #chip southbridge/amd/hudson
+
+ device pci 18.0 on end
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ device pci 18.4 on end
+ device pci 18.5 on end
+
+ register "spdAddrLookup" = "
+ {
+ { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses
+ { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses
+ }"
+
+ end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex
+ end #domain
+end #chip northbridge/amd/agesa/family15tn/root_complex
diff --git a/src/mainboard/asus/f2a85-m_pro/dsdt.asl b/src/mainboard/asus/f2a85-m_pro/dsdt.asl
new file mode 100644
index 0000000..b27b81d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/dsdt.asl
@@ -0,0 +1 @@
+#include "../f2a85-m/dsdt.asl"
diff --git a/src/mainboard/asus/f2a85-m_pro/irq_tables.c b/src/mainboard/asus/f2a85-m_pro/irq_tables.c
new file mode 100644
index 0000000..7e6c693
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/irq_tables.c
@@ -0,0 +1 @@
+#include "../f2a85-m/irq_tables.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/mainboard.c b/src/mainboard/asus/f2a85-m_pro/mainboard.c
new file mode 100644
index 0000000..d8cc9c8
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/mainboard.c
@@ -0,0 +1 @@
+#include "../f2a85-m/mainboard.c"
diff --git a/src/mainboard/asus/f2a85-m_pro/mptable.c b/src/mainboard/asus/f2a85-m_pro/mptable.c
new file mode 100644
index 0000000..1d0784d
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/mptable.c
@@ -0,0 +1 @@
+#include <mainboard/asus/f2a85-m/mptable.c>
diff --git a/src/mainboard/asus/f2a85-m_pro/romstage.c b/src/mainboard/asus/f2a85-m_pro/romstage.c
new file mode 100644
index 0000000..001bae4
--- /dev/null
+++ b/src/mainboard/asus/f2a85-m_pro/romstage.c
@@ -0,0 +1,134 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 Rudolf Marek <r.marek at assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/amd/agesa/agesawrapper.h>
+
+#include <arch/acpi.h>
+#include <arch/cpu.h>
+#include <arch/io.h>
+#include <arch/stages.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <cpu/amd/agesa/s3_resume.h>
+#include <cpu/amd/car.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <device/pnp_def.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>
+#include <superio/nuvoton/common/nuvoton.h>
+#include <superio/nuvoton/nct6779d/nct6779d.h>
+#include <stdint.h>
+#include <string.h>
+
+#define MMIO_NON_POSTED_START 0xfed00000
+#define MMIO_NON_POSTED_END 0xfedfffff
+#define SB_MMIO 0xFED80000
+#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x))
+
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP1)
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+ u8 byte;
+ device_t dev;
+
+#if IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)
+ hudson_pci_port80();
+#endif
+#if IS_ENABLED(CONFIG_POST_DEVICE_LPC)
+ hudson_lpc_port80();
+#endif
+
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+
+ /* enable SIO LPC decode */
+ dev = PCI_DEV(0, 0x14, 3);
+ byte = pci_read_config8(dev, 0x48);
+ byte |= 3; /* 2e, 2f */
+ pci_write_config8(dev, 0x48, byte);
+
+ /* enable serial decode */
+ byte = pci_read_config8(dev, 0x44);
+ byte |= (1 << 6); /* 0x3f8 */
+ pci_write_config8(dev, 0x44, byte);
+
+ post_code(0x30);
+
+ /* enable SB MMIO space */
+ outb(0x24, 0xcd6);
+ outb(0x1, 0xcd7);
+
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ console_init();
+
+ /* turn on secondary smbus at b20 */
+ outb(0x28, 0xcd6);
+ byte = inb(0xcd7);
+ byte |= 1;
+ outb(byte, 0xcd7);
+
+ /* set DDR3 voltage */
+ byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
+
+ /* default is byte = 0x0, so no need to set it in this case */
+ if (byte)
+ do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(bist);
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x37);
+ agesawrapper_amdinitreset();
+ post_code(0x39);
+
+ agesawrapper_amdinitearly();
+ int s3resume = acpi_is_wakeup_s3();
+ if (!s3resume) {
+ post_code(0x40);
+ agesawrapper_amdinitpost();
+ post_code(0x41);
+ agesawrapper_amdinitenv();
+ disable_cache_as_ram();
+ } else { /* S3 detect */
+ printk(BIOS_INFO, "S3 detected\n");
+
+ post_code(0x60);
+ agesawrapper_amdinitresume();
+ amd_initcpuio();
+ agesawrapper_amds3laterestore();
+
+ post_code(0x61);
+ prepare_for_resume();
+ }
+
+ post_code(0x50);
+ copy_and_run();
+
+ post_code(0x54); /* Should never see this post code. */
+}
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