[coreboot-gerrit] Patch set updated for coreboot: nb/intel/sandybridge/raminit: Fill SMBIOS type17 info

[Patrick Rudolph (siro@das-labor.org)]

Patrick Rudolph (siro at das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13852

-gerrit

commit a7baed3e0ee63ff5d0f46c3cfb03497e835eae80
Author: Patrick Rudolph <siro at das-labor.org>
Date:   Sun Feb 28 15:24:04 2016 +0100

    nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
    
    Fill minimal info required for SMBIOS type 17.
    Report
     * DIMM size
     * channel
     * rank per DIMM
     * speed in Mhz
     * DIMM type
     * slot
     * manufacturer ID
     * serial
    
    Allows dmidecode to print the current RAM configuration.
    
    Test system:
     * Gigabyte GA-B75M-D3H
     * Intel Pentium CPU G2130
     * Linux 4.3
     * dmidecode 3.0
    
    dmidecode output:
    Handle 0x0005, DMI type 17, 40 bytes
    Memory Device
    	Array Handle: 0x0000
    	Error Information Handle: Not Provided
    	Total Width: 16 bits
    	Data Width: 8 bits
    	Size: 8192 MB
    	Form Factor: DIMM
    	Set: None
    	Locator: Channel-0-DIMM-0
    	Bank Locator: BANK 0
    	Type: DDR3
    	Type Detail: Synchronous
    	Speed: 1600 MHz
    	Manufacturer: Unknown (cd04)
    	Serial Number: None
    	Asset Tag: Not Specified
    	Part Number: F3-1866C9-8GSR
    	Rank: 2
    	Configured Clock Speed: 1600 MHz
    	Minimum Voltage: Unknown
    	Maximum Voltage: Unknown
    	Configured Voltage: Unknown
    
    Handle 0x0006, DMI type 17, 40 bytes
    Memory Device
    	Array Handle: 0x0000
    	Error Information Handle: Not Provided
    	Total Width: 16 bits
    	Data Width: 8 bits
    	Size: 8192 MB
    	Form Factor: DIMM
    	Set: None
    	Locator: Channel-1-DIMM-1
    	Bank Locator: BANK 0
    	Type: DDR3
    	Type Detail: Synchronous
    	Speed: 1600 MHz
    	Manufacturer: Unknown (cd04)
    	Serial Number: None
    	Asset Tag: Not Specified
    	Part Number: F3-1866C9-8GSR
    	Rank: 2
    	Configured Clock Speed: 1600 MHz
    	Minimum Voltage: Unknown
    	Maximum Voltage: Unknown
    	Configured Voltage: Unknown
    
    Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993
    Signed-off-by: Patrick Rudolph <siro at das-labor.org>
---
 src/northbridge/intel/sandybridge/raminit.c | 49 +++++++++++++++++++++++++++--
 1 file changed, 47 insertions(+), 2 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 40089e2..8b54e93 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -27,6 +27,8 @@
 #include <timestamp.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
+#include <memory_info.h>
+#include <smbios.h>
 #include "raminit_native.h"
 #include "sandybridge.h"
 #include <delay.h>
@@ -233,6 +235,48 @@ static void toggle_io_reset(void) {
 }
 
 /*
+ * Fill cbmem with information for SMBIOS type 17.
+ */
+static void fill_smbios17(dimm_info *info)
+{
+	struct memory_info *mem_info;
+	int channel, slot;
+	uint16_t ddr_freq;
+	struct dimm_info *dimm;
+
+	ddr_freq = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100;
+
+	/*
+	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
+	 * table 17
+	 */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info);
+	if (!mem_info)
+		return;
+
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	FOR_ALL_CHANNELS for(slot = 0; slot < NUM_SLOTS; slot++) {
+		dimm = &mem_info->dimm[mem_info->dimm_cnt];
+		if (info->dimm[channel][slot].size_mb) {
+			dimm->ddr_type = MEMORY_TYPE_DDR3;
+			dimm->ddr_frequency = ddr_freq;
+			dimm->dimm_size = info->dimm[channel][slot].size_mb;
+			dimm->channel_num = channel;
+			dimm->rank_per_dimm = info->dimm[channel][slot].ranks;
+			dimm->dimm_num = slot;
+			memcpy(dimm->module_part_number,
+				   info->dimm[channel][slot].part_number, 16);
+			dimm->mod_id = info->dimm[channel][slot].manufacturer_id;
+			dimm->mod_type = info->dimm[channel][slot].dimm_type;
+			dimm->bus_width = info->dimm[channel][slot].width;
+			mem_info->dimm_cnt++;
+		}
+	}
+}
+
+/*
  * Dump in the log memory controller configuration as read from the memory
  * controller registers.
  */
@@ -3884,6 +3928,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
 {
 	int me_uma_size;
 	int cbmem_was_inited;
+	dimm_info info;
 
 	MCHBAR32(0x5f00) |= 1;
 
@@ -3937,8 +3982,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
 	}
 
 	if (!s3resume) {
-		dimm_info info;
-
 		/* Get DDR3 SPD data */
 		dram_find_spds_ddr3(spds, &info, &ctrl);
 
@@ -4065,6 +4108,8 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
 		outb(0x6, 0xcf9);
 		halt();
 	}
+
+	fill_smbios17(&info);
 }
 
 #define HOST_BRIDGE	PCI_DEVFN(0, 0)