[coreboot-gerrit] Patch set updated for coreboot: arch/x86: Allow soc/chipset to set linking address

[Andrey Petrov (andrey.petrov@intel.com)]

Andrey Petrov (andrey.petrov at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13860

-gerrit

commit d83ff340eac20d716d2a445db17d876f3d7b5b89
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Sun Feb 28 22:04:51 2016 -0800

    arch/x86: Allow soc/chipset to set linking address
    
    Until recently x86 romstage used to be linked at some default
    address. The address itself is not meaningful because the code
    was normally relocated at address calculated during insertion
    in CBFS. Since some newer SoC run romstage at CAR it became
    useful to link romstage code at some address in CAR and avoid
    relocation during build/run time altogether.
    
    Change-Id: I11bec142ab204633da0000a63792de7057e2eeaf
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
---
 src/arch/x86/Kconfig      | 10 ++++++++++
 src/arch/x86/memlayout.ld |  4 ++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 89e142a..2257cb6 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -161,3 +161,13 @@ config COMPILE_IN_DSDT
 config C_ENV_BOOTBLOCK_SIZE
 	hex
 	default 0x10000
+
+# Default address romstage is to be linked at
+config ROMSTAGE_ADDR
+	hex
+	default 0x2000000
+
+# Default address verstage is to be linked at
+config VERSTAGE_ADDR
+	hex
+	default 0x2000000
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index fb67575..56611041 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -31,14 +31,14 @@ SECTIONS
 #elif ENV_ROMSTAGE
 	/* The 1M size is not allocated. It's just for basic size checking.
 	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
-	ROMSTAGE(32M, 1M)
+	ROMSTAGE(CONFIG_ROMSTAGE_ADDR, 1M)
 
 	/* Pull in the cache-as-ram rules. */
 	#include "car.ld"
 #elif ENV_VERSTAGE
 	/* The 1M size is not allocated. It's just for basic size checking.
 	 * Link at 32MiB address and rely on cbfstool to relocate to XIP. */
-	VERSTAGE(32M, 1M)
+	VERSTAGE(CONFIG_VERSTAGE_ADDR, 1M)
 
 	/* Pull in the cache-as-ram rules. */
 	#include "car.ld"