Level 2 cache activation code?
svante.signell at telia.com
Fri Nov 14 01:53:01 CET 2003
I have now run the lmbench3-0-a3 tests. For the correctly working 1.4
GHz Tualatin CPU the latency numbers shows jumps from 2ns to 6ns at 16k
array size and from 6ns to 120ns at 265k array size. I assume this
indicates correctly working level 1 and 2 caches.
For the erroneous motherboard with a 1.3GHz Tualatin CPU the numbers are
around 400ns independent of array size. The only thing changig is that
the latency numbers increase to 440-460ns for large values of the
stride. My interpretation is that not even the L1 cache is working
properly. All other tests indicate a _very_ slow CPU, around 7MHz is
measured by lmbench (BTW how good is this value?) compared to the
expected 1.3GHz. Two questions immediately arise.
1. Is this slowness reasonable if _no- caches are working properly?
2. If there is a problem with the on-chip voltage regulator and the CPU
clock speed is really 7MHz, as measured by lmbench, can the CPU operate
properly at this low speed. I thought there was a _lower_ limit as well
as an upper limit for the operating frequency?
On Fri, 2003-11-07 at 06:04, ron minnich wrote:
> Those lm bench memory tests with the plots of memory access times will
> show you l1, l2, and memory boundaries.
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> Linuxbios at clustermatic.org
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