[coreboot] [PATCH] artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size)
mart.raudsepp at artecdesign.ee
Wed Aug 13 15:33:01 CEST 2008
Ühel kenal päeval, T, 2008-08-12 kell 20:02, kirjutas ron minnich:
> ok, bad news. With that setting, my board never gets past dram init.
> If you have more than one dbe62 board working with this setting, I'm
> prepared to say I've got a busted board/dram chip/whatever.
I chatted with Martin-Eric, and he is quite confident you have a DBE62
with 128MB of RAM, as the unit that you received was an early prototype.
Almost all other DBE62's in circulation have 256MB, including the one
I'm working on. So I bet that is the issue here.
Did we miss the difference or forget this back when we were looking for
memory chip specification docs and told what memory chip model my units
here have and you told mine?
This also means the registers I gave you were for 256MB, while running
it on a 128MB unit might have resulted in automatically different
registry settings in our firmware - you can probably get those with the
LinuxBIOS firmware you have now.
What we need for DBE61 anyway, is ability to provide multiple SPD's to
try out - because DBE61 has various memory configurations in the wild -
128MB, 256MB, etc. But for the same RAM amount it uses always the same
memory chips, so it boils down to supporting doing what we do in our
code --> Set it up with the largest size, try writing to the highest
addresses, if it succeeds continue and if it fails try the lower amount
of RAM timings, etc. In coreboot-v3 Kconfig system we can also have a
DBE61 specific setting for RAM size, defaulting to "automatic" that does
this described testing, while those who build the image themselves for a
certain unit with known RAM size can select the right one and not have
it waste a few milliseconds on trying various.
Then we can also do the same with DBE62 - with 256MB for all units, and
128MB for the very few prototype units, of which one is what you have
with 128MB (do you?)
Artec Design LLC
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