[coreboot] r820 - in coreboot-v3: mainboard/amd/serengeti southbridge/amd/amd8111

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Mon Aug 25 00:38:17 CEST 2008

On 24.08.2008 23:39, ron minnich wrote:
> it's actually very simple. Stage0 needs to grow -- we might as well
> grow to 32768 and see how it goes.
> It's also a bug. stage0 code is being truncated to 20480 bytes with on
> warning. The pci_find_device function could extend past ffffffff0, but
> it gets truncated in the middle -> triple fault.

Oh, I got an even worse stage0 layout during my quest to trigger linker
bugs. Only code changes in stage1.c, no linker script was touched:
ffffec36 T set_bios_reset
ffffec59 T distinguish_cpu_resets
ffffec80 T _stage0
ffffecb0 t gdt16x
ffffecc8 T gdtptr
ffffecc8 t gdt
ffffecc8 t gdt16xend
ffffecf0 T protected_stage0
ffffecf0 t gdt_end
ffffecff T __protected_stage0
ffffed17 t cache_as_ram_setup
ffffed29 t enable_fixed_mtrr_dram_modify
ffffed43 t clear_fixed_var_mtrr
ffffed50 t clear_fixed_var_mtrr_out
ffffede2 t fixed_mtrr_msr
ffffee0e t var_mtrr_msr
ffffee4e t var_iorr_msr
ffffee5e t mem_top
ffffee6a t cache_as_ram_setup_out
fffff6f0 t algo_name
fffff704 t console_test.1860
fffff758 t foo
fffff900 T option_table
fffffff0 A _ROMTOP
fffffff0 T _resetjump
fffffff0 t pow2_to_link_width.2169
fffffff8 t link_width_to_pow2.2168

Especially the last three lines are VERY disturbing. And no warning is
triggered at all. It seems the linker doesn't even notice that it
allocated the same space twice.

Having algo_name, the console test banner and the option table between
stage0 asm and the reset vector also bothers me.



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