[coreboot] Resource allocation
mylesgw at gmail.com
Tue Nov 11 18:33:47 CET 2008
> -----Original Message-----
> From: Marc Jones [mailto:marcj303 at yahoo.com]
> Sent: Tuesday, November 11, 2008 10:12 AM
> To: Myles Watson; Coreboot; ron minnich
> Subject: Re: [coreboot] Resource allocation
> ----- Original Message ----
> > From: Myles Watson <mylesgw at gmail.com>
> > To: Marc Jones <marcj303 at yahoo.com>; Coreboot <coreboot at coreboot.org>;
> ron minnich <rminnich at gmail.com>
> > Sent: Tuesday, November 11, 2008 7:42:57 AM
> > Subject: RE: [coreboot] Resource allocation
> > > > My question is if resources ever split. In other words, lets
> imagine a
> > > > device which implements several IO ports in the 0x3fX range and
> > > > regions that must be mapped above 0x1000. Since the limit for the
> > > smaller
> > > > regions is 0x7ff and the alignment for the larger regions is 0x1000,
> > > they
> > > > both can't coexist.
> > > >
> > > > What happens?
> > >
> > > Everything
> > > below 0x1000 is legacy IO space and are not typically used by PCI
> > > devices (some devices/firmware sneek some stuff in around 0x800 for
> > > ACPI). As you noted there are some devices that might need to decode
> > > legacy regions to boot. If that is the case they will usually have a
> > > legacy enable bit in the header. In legacy mode the PCI BARs are
> > > ignored. The firmware, option ROM, and driver need to be aware of
> > > mode it is in. An example is the AMD sb600 IDE controller(Device 20,
> > > Function 1). There is a legacy/PCI mode in the revision register ot
> > > offset 0x8.
> > Thanks Marc.
> > All right. So the legacy IO resources shouldn't be grouped with the
> > Should they be marked Subtractive? Are they declared to be special in a
> > different way?
> Yes but those legacy addresses could be positively decoded anywhere along
> the subtractive path. They will usually go as far as the chipset with an
> integrated controller. So, if someone put a legacy IDE controller farther
> on the path it (like lpc) it would never get the IO. For completeness in
> the dts you could have all the addresses in the system but I don't know if
> it is that important. I guess we need to add legacy io reserve code to the
> chipsets similar to the SIOs.
Thanks for the help; sorry to be dense. Could we flesh this out a little
The problem I'm having is that the SuperIO is declaring several resources,
some of which are below the 0x1000 threshold, and some of which are not.
They are all declared to be IO, so they need to fit in the same bridge
resource, and can't. If they were a different type, or if they were ignored
by the resource code, it could still work.
I understand that the subtractive decode and VGA bits need to be set on the
bridge (amd8111), but I don't know how we protect the legacy IDE area if
someone added an IDE card to the PCI bus of the amd8111.
> Note that the exception to the subtractive decode is the VGA snoop and VGA
> enable (just for legacy VGA registes 0x3Cx -0x3Dx I think).
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