[coreboot] r1056 - in coreboot-v3/arch/x86: . intel/core2
c-d.hailfinger.devel.2006 at gmx.net
Thu Nov 27 21:51:20 CET 2008
On 26.11.2008 00:10, svn at coreboot.org wrote:
> Author: stepan
> Date: 2008-11-26 00:10:24 +0100 (Wed, 26 Nov 2008)
> New Revision: 1056
> hack to make v3 rom access a lot faster.
> Signed-off-by: Stefan Reinauer <stepan at coresystems.de>
> Acked-by: Stefan Reinauer <stepan at coresystems.de>
This commit likely breaks support for some Core 2 processors (it will
make CAR fail due to random eviction of cache lines) and I believe it
was the reason why the tree didn't work anymore for Stefan.
CAR is 32k cache. (unchanged)
XIP is 1024k cache. (new)
Cache types for both are the same. On a processor with 1024k cache (Core
2 Solo), this will cause CAR and XIP not to fit into the cache together.
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