[coreboot] Problems porting H8dmr_fam10 to H8qme-2+

Knut Kujat knuku at gap.upv.es
Wed Dec 30 11:09:05 CET 2009

Myles Watson escribió:
>>> Unfortunately, it's undocumented, so you have a couple of options:
>>> 1. Look at http://www.coreboot.org/Nvidia_MCP55_Porting_Notes
>>> 2. Decode the ACPI interrrupt assignments
>>> Either way you may need to look at the interrupt assignments in Linux
>>> when booted with the factory BIOS.
>> I'm wondering if it isn't possible to just read those registers out once
>> booted with a factory BIOS?
> You can.  You still have to make the mptable and irq table match, which
> requires you to know what the values mean.
at irq table you mean this values:

write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); <<< this

    pirq_info++; slot_num++;
    for(i=1; i< sysconf.hc_possible_num; i++) {
        if(!(sysconf.pci1234[i] & 0x1) ) continue;
        unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
        unsigned devn = sysconf.hcdn[i] & 0xff;

        write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2,
0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);  <<< and this.
        pirq_info++; slot_num++;

Sorry for those noob questions but this is getting much deeper i thought
it would go. ;)

>> Using SeaBios 5.0 it "accepts" level 8 for debugging, but still no luck
>> with the vga initialization. It doesn't even seem to be SeaBios "fault"
>> because Coreboot complains exactly the same story:
>> PCI: 01:01.0 init
>> CBFS:  Could not find file pci1002,515e.rom
> You could read the ROM, correct the signature, and put it in CBFS as
> pci1002,515e.rom
>> On card, rom address for PCI: 01:01.0 = fc000000
>> PCI Expansion ROM, signature 0x7373, INIT size 0xe600, data ptr 0x7373
>> Incorrect Expansion ROM Header Signature 7373
> You're right.  It looks like the signature in your ROM is not coming out
> correctly.  You need to figure out why, or just try to ignore the bad
> signature and see if you can get past it.  In Linux with the factory BIOS
> you could see if the signature is still broken.
OK I'll will first try to make my irqs work after. Because I think most
of the trouble is coming from there.
One difference I noticed between my lspci -tvnn output and coreboot is
that the ati es 1000 is at bus 6 on the lspci output and on bus 7 at

 +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
             +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
             +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
             +-06.0-[01]----01.0  ATI Technologies Inc ES1000 [1002:515e]


PCI: 00:07.0 resource base 0 size 0 align 20 gran 20 limit ffffffff
flags 80202 index 20
     PCI: 01:01.0 links 0 child on link 0 NULL
     PCI: 01:01.0 resource base 0 size 8000000 align 27 gran 27 limit
ffffffff flags 1200 index 10
     PCI: 01:01.0 resource base 0 size 100 align 8 gran 8 limit ffff
flags 100 index 14
     PCI: 01:01.0 resource base 0 size 10000 align 16 gran 16 limit
ffffffff flags 200 index 18
     PCI: 01:01.0 resource base 0 size 20000 align 17 gran 17 limit
ffffffff flags 2200 index 30

Is this just a different kind of enumeration or an error?

thx again, again and again,
Knut Kujat.

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