[coreboot] flashrom SB600 LPC vs SPI, ROM straps

Bao, Zheng Zheng.Bao at amd.com
Wed Feb 4 06:06:45 CET 2009

That is why I send the patch which removes code that "unconditionally
enables SPI in the PM registers". If the SPI commands failed, it will go
on probing other chips. And then it will find the LPC flashchip which it
should work with.


-----Original Message-----
From: coreboot-bounces at coreboot.org
[mailto:coreboot-bounces at coreboot.org] On Behalf Of Peter Stuge
Sent: Wednesday, February 04, 2009 12:28 PM
To: coreboot at coreboot.org
Cc: Perley, Tim
Subject: Re: [coreboot] flashrom SB600 LPC vs SPI, ROM straps

Bao, Zheng wrote:
> About 2, we don't have to know where the board boots.

I'm afraid we do.

> If we assume the cross-burning is not allowed, the flashrom can not
> detect the existence of a SPI chip. Then it will not do any SPI
> action. Right?

The flashbus variable is used to control if and how SPI commands are
performed by flashrom.

Existing chipset enable code for SB600 unconditionally enables SPI in
the PM registers, and sets flashbus = BUS_TYPE_SB600_SPI. This does
not work, as can be seen on SB600 boards with LPC flash. Leaving the
PM registers untouched and setting flashbus = BUS_TYPE_SB600_SPI also
does not work, because erase and probe commands will be sent via SPI.

flashrom must detect what the system is actually using so that the
flashbus variable is set correctly.


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