[coreboot] flashrom SB600 LPC vs SPI, ROM straps
peter at stuge.se
Wed Feb 4 07:50:38 CET 2009
Bao, Zheng wrote:
> That is why I send the patch which removes code that
> "unconditionally enables SPI in the PM registers". If the SPI
> commands failed, it will go on probing other chips. And then it
> will find the LPC flashchip which it should work with.
SPI commands will hang if there is no SPI flash chip so they must
not be used blindly. Do you know what state the SPI hardware will
be in if an SPI command is executed without an SPI flash chip?
>> Leaving the PM registers untouched and setting
>> flashbus = BUS_TYPE_SB600_SPI also does not work, because
>> erase and probe commands will be sent via SPI.
Please consider this again. By "leave untouched" I mean that flashrom
does not set these registers, as in your suggested patch. If flashbus
is set to BUS_TYPE_SB600_SPI, sb600_spi_ functions will be called.
The way flashrom is written, each function can not fall back to
direct CPU access. The flashbus variable was introduced to control
this exact thing and it needs to be set to reflect the hardware.
>> flashrom must detect what the system is actually using so that the
>> flashbus variable is set correctly.
Unfortunately we can not get around this. For flashrom to do the
right thing, we must check (or worst case, guess) what the system is
SPI command timeout is not as good indication as if we can find out
the value of the ROM strap through other means. Maybe there is even
risk that issuing a command that hangs has a negative effect on the
LPC/SPI state. In particular, I am worried about the SPI/LPC
translation that SB600 can do which transparently allows the MAC
access to an LPC flash chip via SPI.
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