[coreboot] intel p6 core msrs

Holger Hesselbarth popkonserve at gmx.de
Sat Feb 7 12:53:27 CET 2009

just for a start here is my first real contribution.
here are some answers to questions that Peter Stuge asked..

  >> 		{ 17, 5, "L2PBS", "L2 size per bank", PRESENT_DEC, {
  >> 			{ MSR1(0), "128 kbytes" },
  >> 			{ MSR1(1), "256 kbytes" },
  >> 			{ MSR1(2), "512 kbytes" },
  >> 			{ MSR1(4), "1 Mbytes" },
  >> 			{ MSR1(8), "2 Mbytes" },
  >> 			{ MSR1(16), "4 Mbytes" },
  >> 			{ BITVAL_EOT }
  >> 		}},
  > Hmm, can you explain this field a little more? Will only one bit ever
  > be set at a time?

there's no real info on this in the intel documents i have. welcome to intel's
msr mystery world :( but based on the available processors with p6 core we can
assume this: only one bit will be set or none. the intel celerons have 128kB L2
cache unless they are tualatin cores, then they'll have 256kB cache. all intel
pentium ii have 512kB L2 cache. all pentium iii processors have 512kB L2 cache
unless they are coppermine, then they'll have 256kB. pentium iii tualatins have
512kB L2 cache again. xeons with drake core(derived from pentium ii deschutes)
have 512kB, 1MB or 2MB cache. tanner (derived from pentium iii katmai) core
xeons have 1MB or 2MB cache while the cascades cores (derived from pentium iii
coppermine) have 256kB (!!!) or 2MB cache.
i hope you are not too confused by now.

>>         { 4, 4, "L2LAT", "L2 latency", PRESENT_DEC, NOBITS },
> ..and here. Btw, what unit is this latency expressed in?

the latency is expressed in intel mystery units. since the docs don't say
anything about the units, my guess is the following. it's in units of cycles of
the bus speed of the L2 cache bus. on some of the pentium iis and pentium iiis
the L2 cache was off-chip but on-module. there the latency makes sense and it
was set to 5 (according to intel's recommendations?). on later models the cache
went on-chip and the L2 cache latency went down to 1. on abit slot 1 boards the
cache latency could be adjusted, too.

> A target definition has to be added to msrtool.c as well. A super
> simple entry in struct targetdef alltargets[].

i called it P6 since that's what Intel calls this specific processor core in
their offical documents. and this msr declaration is for P6 cores only. some tme
later it should contain all msrs from the P6 core. but you are free to suggest a
better name :)

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