[coreboot] Coreboot patches for v2 with SeaBIOS

Rudolf Marek r.marek at assembler.cz
Fri Feb 13 22:27:39 CET 2009

> I wasn't clear.  I needed the address for the fadt pm_base.  Since
> coreboot allocates it at 0x1000 and the factory BIOS allocates it at
> 0x8000 I was having a hard time finding it.

OK hopefully it is static ;)

> Do you get that error too, or was I supposed to change some value to
> make it work?

Perhaps something was missing? I dont know. Lets solve this later.

> It is 0.


>> for SATA 0 the _PR looks like this:
>>  Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x17 }, //sata at 7.0 goes to IRQ
>> 23
> Thanks, that helped a lot.  I'm still not booting though.  I get this
> error in the boot log, then the hard drives stop working.  The
> interrupts shouldn't be at fault, because they match the mptable.
>  ..TIMER: vector=0x30 apic1=0 pin1=0 apic2=-1 pin2=-1
>  ..MP-BIOS bug: 8254 timer not connected to IO-APIC
>  ...trying to set up timer (IRQ0) through the 8259A ...
>  ..... (found apic 0 pin 0) ...
>  ....... failed.
>  ...trying to set up timer as Virtual Wire IRQ...
>  ..... failed.
>  ...trying to set up timer as ExtINT IRQ...
>  ..... works.
> Here's the first line from the acpi=off boot:
>  ..TIMER: vector=0x30 apic1=0 pin1=0 apic2=0 pin2=0
> Unfortunately I can't see where it gets set to correct it.

Aha you need also a MADT table. It seems this table is bit mess:

This is for IRQ9 to be the ACPI irq level low triggered:

+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+						current, 0, 9, 9, 0xF);

You need this:

         /* IRQ0 -> APIC IRQ2. */
         current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
                                                 current, 0, 0, 2, 0x0);

Check the original BIOS whats inside the MADT  please.

the first zero is 0 which is ISA bus. The second 0 is bus relative source of IRQ 
- IRQ0 in our case. But IRQ0 is not mapped to IRQ0 but to pin2 on APIC so We 
create a mapping of IRQ0->IRQ2

Also this is also wrong:
/* Write NVIDIA CK804 IOAPIC. */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 4,
+					   IO_APIC_ADDR, 0);
+	/* Write AMD 8131 two IOAPICs. */
+	/* FIXME should find device and ask for address! */
+	apic_addr = 0xfc200000;
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 5,
+					   apic_addr, 0);
+	apic_addr = 0xfc201000;
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 6,
+					   apic_addr, 0);

The last parameter of both APIC cannot be 0, it must be the offset called 
"system vector base" usually if the first apic has 24 inputs. Second base starts 
at 24... This just put the numbers in _PRT to relationship in what APIC is what 
global IRQ  (sometimes called GSI)

Good is a figure on page 138 (in pdf) in acpi 3.0 specs. You will get it quickly 
once looking to the picture.

Also very good is a picture in MP specs which shows how the 8259 and apics are 

http://www.intel.com/design/pentium/datashts/24201606.pdf Its on page 65.

There you see why the IRQ2 override is neccessary. The bus 0 which is ISA has 
identity mappings of 8259 IRQs 0-15 to apic pins 0-15 with exception of 
IRQ0(APIC) where no timer is connected but the output from 8259s. The IRQ2 
(pin2) on APIC is used as IRQ0(ISA)

I think there is a chance that it will start to work. You will also need to put 
the APIC in SB to virtual wire mode, so the 8259 can be used. (This is for DOS, 
I think linux needs that only for a while)


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