[coreboot] Coreboot patches for v2 with SeaBIOS

Rudolf Marek r.marek at assembler.cz
Tue Feb 17 21:59:35 CET 2009


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Hi,
>  ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>  ACPI: BIOS IRQ0 pin2 override ignored.

OK maybe it belongs to another APIC dont know. Maybe just ignore this.
> Looking at this made me remember that only PCI0 gets parsed by the
> kernel.  I don't know why it skips the other root buses.

Do you have them in DSDT? Please post your current DSDT.
You will need also some another device for second PCI bus.


> 
> As long as I make it match the mptable, shouldn't it just work?

It should.

> Right now I can't get it to match because the other busses are never
> parsed so those PRT entries are ignored.


Check this FAQ:
http://www.acpi.info/acpi_faq.htm

Q: But how about a multiple root bus machine? How do I report several CPU-to-PCI
bridges (root PCI Buses) in the ACPI NameSpace?

You will need _BBN  object.

Thanks,
Rudolf
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