[coreboot] ASUS M2N-SLI Deluxe
mylesgw at gmail.com
Fri Jan 2 22:36:34 CET 2009
> -----Original Message-----
> From: coreboot-bounces+mylesgw=gmail.com at coreboot.org [mailto:coreboot-
> bounces+mylesgw=gmail.com at coreboot.org] On Behalf Of Christian Ruppert
> Sent: Friday, January 02, 2009 11:51 AM
> To: coreboot at coreboot.org
> Subject: Re: [coreboot] ASUS M2N-SLI Deluxe
> ok guys,
> a little summary from my side:
> i've tried the patch from uwe  but there are some issues with the
> baud rate and also the same problem as fred  had but with a
> different output.
> the baud problem could be solved with a small workaround: just change
> to 57600 in minicom but leave 115200 in the bios source.
> uwe wrote then a second patch (see attachment, works with the lastest
> svn rev. (remove the old patch before apply the new one)) which fixed
> the baud problem and other stuff but not the "poweroff" problem.
> my first boot log was:
> coreboot-126.96.36.199Fallback Fr 2. Jan 17:10:59 CET 2009 starting...
> *sysinfo range: [000cf000,000cf730)
> Enabling routing table for node 00 done.
> Enabling UP settings
> core0 started:
> started ap apicid: 01
> NC node|link=00
> begin msr fid, vid 3107121207110202
> Current fid_cur: 0x2, fid_max: 0x11
> Requested fid_new: 0x11
> FidVid table step fidvid: 0xe
> 200MHZ step fidvid: 0x10
> 100MHZ step fidvid: 0x11
> end msr fid, vid 3107120707110211
> entering optimize_link_incoherent_ht
> entering ht_optimize_link
> pos=0x8a, unfiltered freq_cap=0x8075
> pos=0x8a, filtered freq_cap=0x75
> pos=0x52, unfiltered freq_cap=0x807f
> pos=0x52, filtered freq_cap=0x7f
> freq_cap1=0x75, freq_cap2=0x7f
> dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
> dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
> width_cap1=0x11, width_cap2=0x11
> dev1 input ln_width1=0x4, ln_width2=0x4
> dev1 input width=0x1
> dev1 output ln_width1=0x4, ln_width2=0x4
> dev1 input|output width=0x11
> old dev1 input|output width=0x11
> dev2 input|output width=0x11
> old dev2 input|output width=0x11
> after ht_optimize_link for link pair 0, reset_needed=0x1
> after optimize_link_read_pointers_chain, reset_needed=0x1
It looks like you're getting to the first reset, then that isn't working.
Have you tried commenting out the reset at that point to see how much
farther you get?
The reset is to make the HT optimizations take effect, so it will be slower
but should continue.
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