[coreboot] cbfs XIP patch
mylesgw at gmail.com
Tue May 5 19:54:04 CEST 2009
On Tue, May 5, 2009 at 11:50 AM, Peter Stuge <peter at stuge.se> wrote:
> ron minnich wrote:
>> > 'next' foils the desirable property that single files in cbfs can
>> > be updated in the flash chip without touching any other regions.
>> Isn't this somewhat mythical anyway?
> No sir.
>> how many flash chips support 'erase byte' at this point (I honestly
>> don't know!). I.e., isn't an update of any one byte in a block
>> going to wipe out a whole block? How many cbfs files fit on neat
>> 64k or 16k or whatever boundaries?
> None have single byte erase blocks, but most of the SPI flash chips
> can actually do 256 byte erase blocks.
Since erase block granularity is chip dependent, shouldn't flashrom be
in charge of touching the minimal number of blocks? I don't see how
CBFS can know which chip it will be used in.
> I think it is important to keep the alignment in mind, so that files
> can be fit onto boundaries. I also think we should try to do it in
> the normal case.
What's the most common boundary? 1K, 2K, 4K? Should we pick one that
> I keep imagining how I will be able to safely update the coreboot
> normal image but keep fallback, stages and payloads untouched.
That would be nice.
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