[coreboot] [PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds
Myles Watson
mylesgw at gmail.com
Sat May 9 05:42:17 CEST 2009
On Thu, May 7, 2009 at 6:45 PM, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006 at gmx.net> wrote:
> Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
> commands take around 10 microseconds to complete, it is totally
> pointless to wait for 1000 microseconds before checking the status again.
>
> This patch is tested and reduced write time on ICH7 with SST25VF080B
> from over one hour to 62 seconds.
>
> Thanks to Ali Nadalizadeh for testing!
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Myles Watson <mylesgw at gmail.com>
I like the 1 hour to 62 seconds.
Thanks,
Myles
>
> Index: flashrom-ichspi_delay/ichspi.c
> ===================================================================
> --- flashrom-ichspi_delay/ichspi.c (Revision 471)
> +++ flashrom-ichspi_delay/ichspi.c (Arbeitskopie)
> @@ -458,9 +458,9 @@
> REGWRITE16(ICH7_REG_SPIC, temp16);
>
> /* wait for cycle complete */
> - timeout = 1000 * 60; // 60s is a looong timeout.
> + timeout = 100 * 1000 * 60; // 60s is a looong timeout.
> while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
> - myusec_delay(1000);
> + myusec_delay(10);
> }
> if (!timeout) {
> printf_debug("timeout\n");
> @@ -575,9 +575,9 @@
> REGWRITE32(ICH9_REG_SSFS, temp32);
>
> /*wait for cycle complete */
> - timeout = 1000 * 60; // 60s is a looong timeout.
> + timeout = 100 * 1000 * 60; // 60s is a looong timeout.
> while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
> - myusec_delay(1000);
> + myusec_delay(10);
> }
> if (!timeout) {
> printf_debug("timeout\n");
>
>
> --
> http://www.hailfinger.org/
>
>
> Index: flashrom-ichspi_delay/ichspi.c
> ===================================================================
> --- flashrom-ichspi_delay/ichspi.c (Revision 471)
> +++ flashrom-ichspi_delay/ichspi.c (Arbeitskopie)
> @@ -458,9 +458,9 @@
> REGWRITE16(ICH7_REG_SPIC, temp16);
>
> /* wait for cycle complete */
> - timeout = 1000 * 60; // 60s is a looong timeout.
> + timeout = 100 * 1000 * 60; // 60s is a looong timeout.
> while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
> - myusec_delay(1000);
> + myusec_delay(10);
> }
> if (!timeout) {
> printf_debug("timeout\n");
> @@ -575,9 +575,9 @@
> REGWRITE32(ICH9_REG_SSFS, temp32);
>
> /*wait for cycle complete */
> - timeout = 1000 * 60; // 60s is a looong timeout.
> + timeout = 100 * 1000 * 60; // 60s is a looong timeout.
> while (((REGREAD32(ICH9_REG_SSFS) & SSFS_CDS) == 0) && --timeout) {
> - myusec_delay(1000);
> + myusec_delay(10);
> }
> if (!timeout) {
> printf_debug("timeout\n");
>
> --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
>
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