[coreboot] [PATCH] VIA C7 CAR fixes / cleanup

[Kevin O'Connor]

On Sun, Apr 11, 2010 at 11:22:14PM -0400, Kevin O'Connor wrote:
> Old code timing (r5005 with caching hacks):
> 
> 00.000: <00>
> 00.006: <00>
> 00.343: 
> 00.343: 
> 00.343: coreboot-2.3" Fri Jan  8 20:36:20 EST 2010 starting...
> 00.344: *pre enable_smbus()
> 00.402: *post enable_smbus()
> 00.406: *pre ddr_ram_setup()
> 00.422: *post ddr_ram_setup()
> 00.424: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000
> 00.450: coreboot-2.3 Fri Apr  2 11:56:00 EDT 2010 booting...
> 
> New code timing (r5408):
> 
> 00.000: <00>
> 00.446: 0
> 00.448: 
> 00.448: coreboot-4.0-r5408M Sun Apr 11 22:51:47 EDT 2010 starting...
> 00.448: *pre enable_smbus()
> 00.448: *post enable_smbus()
> 00.452: *pre ddr_ram_setup()
> 00.464: *post ddr_ram_setup()
> 00.465: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000
> 01.421: coreboot-4.0-r5408M Sun Apr 11 22:51:47 EDT 2010 booting...
[...]
> The extra time to get to the "coreboot-..." banner is a bit puzzling
> though.  The timings are reproducible, so it's not a fluke.  I'll have
> to investigate further.

The extra time to get to the "coreboot-..." banner is due to the "rep
lodsl" insns that populate the cache in
src/cpu/via/car/cache_as_ram.inc.  I don't think the second "rep
lodsl" (that prefetches the rom) is needed - commenting it out gives
better timings:

00.000: <00>
00.005: <00>
00.388: 0
00.389: 
00.389: coreboot-4.0-r5408M Mon Apr 12 00:19:03 EDT 2010 starting...
00.390: *pre enable_smbus()
00.398: *post enable_smbus()
00.398: *pre ddr_ram_setup()
00.412: *post ddr_ram_setup()
00.415: Stage: loading fallback/coreboot_ram @ 0x4000 (163840 bytes), entry @ 0x4000
01.369: coreboot-4.0-r5408M Mon Apr 12 00:19:03 EDT 2010 booting...

Indeed, the time to "Stage:..." is faster than romcc now.  Just need
to fix that delay after "Stage:"..

-Kevin