[coreboot] Patch merged into coreboot/master: 08500eb Intel cpus: Extend cache to cover complete Flash Device

gerrit at coreboot.org gerrit at coreboot.org
Wed Jul 4 14:50:29 CEST 2012

the following patch was just integrated into master:
commit 08500ebe42116adc95bd2db59948e0d6197903fb
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Sat Jun 30 11:41:08 2012 +0300

    Intel cpus: Extend cache to cover complete Flash Device
    CACHE_ROM_SIZE default is ROM_SIZE, the Flash device size set
    in menuconfig. This fixes a case where 8 MB SPI flash MTRR setup
    would not cover the bottom 4 MB when ramstage is decompressed.
    Verify CACHE_ROM_SIZE is power of two.
    One may set CACHE_ROM_SIZE==0 to disable this cache.
    Change-Id: Ib2b4ea528a092b96ff954894e60406d64f250783
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>

Build-Tested: build bot (Jenkins) at Wed Jul  4 11:32:26 2012, giving +1
Reviewed-By: Sven Schnelle <svens at stackframe.org> at Wed Jul  4 14:47:23 2012, giving +2
See http://review.coreboot.org/1146 for details.


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