[coreboot] Dual SPI Flash
peter at stuge.se
Tue Mar 6 19:33:39 CET 2012
Oliver Schinagl wrote:
> Pin 1, 'chip select enable' is an inverted? pin. enables and
> disables device operation. When chip select is high, the device is
> de-selected and the serial data pins are at 'high impedance'.
> So if I understand all this correctly, the chip can be
> connected in parallel with the exception of the Chip Select Enable.
> A simple switch to either connect it directly to the
> board/socket/other end and toggle it to connect to ground (via
> 'some' resistor').
Right. This is what you can see demonstrated in the photos linked to
at the bottom of http://stuge.se/m57sli/ i.e.:
These photos are not from a PC mainboard but the principle hopefully
shows. The connection you describe is indeed how GIGABYTE boards
implement Dual BIOS. What is not shown in my photos are the
resistors, which are mounted onto the GIGABYTE board on pads for that
> I tried to make a simple schematic in ascii, but failed horribly so i've
> attached it to this message as monochrome BMP (only format that I could
> quickly think of to be smallest in size).
> I don't know what value those resistors need to be (and if the
> schematic can be even more simplified, with a single resistor), but
> I belive this is the schematic used for the dual-SPI flash 'module'
Not quite, the resistors need to be pull-up and not pull-down. See
e.g. http://stuge.se/flash_switch.png which shows the principle with
resistors, but connects the switch common to GND, instead of to the
mainboard as must be done.
> This seems sensible to me, but my knowledge in
> this field is very limited.
You're already learning more. Your schematic is correct, but
resistors need to pull up to 3.3V and not down to GND. The values
are, as I wrote earlier, not really critical, just don't go too
much under 1k or you will potentially waste some current.
Also make sure that your switch is the break-before-make type.
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