[coreboot] New patch to review for coreboot: 6e5a8d2 Correct FSB reading in speedstep ACPI

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Tue Oct 30 14:50:11 CET 2012


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1656

-gerrit

commit 6e5a8d23dff4c96065f4a67b25cad4897dd26f8e
Author: Nico Huber <nico.huber at secunet.com>
Date:   Thu Sep 6 17:46:30 2012 +0200

    Correct FSB reading in speedstep ACPI
    
    We parsed the MSR the wrong way, and didn't support some valid values.
    
    Change-Id: Ia42e3de05dd76b6830aaa310ec82031d36def3a0
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/cpu/intel/speedstep/acpi.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 249d9e4..d658c70 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -49,13 +49,15 @@ static int determine_total_number_of_cores(void)
 
 static int get_fsb(void)
 {
-	u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
+	const u32 fsbcode = rdmsr(0xcd).lo & 7;
 	switch (fsbcode) {
 		case 0: return 266;
 		case 1: return 133;
 		case 2: return 200;
 		case 3: return 166;
+		case 4: return 333;
 		case 5: return 100;
+		case 6: return 400;
 	}
 	printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
 	return 200;




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