Board:hp/pavilion m6 1035dx
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Hello. I'll have some more info soon enough. For now, remember this:
$ flashrom -pinternal:amd_imc_force=yes -w coreboot.rom
Now chances are that will brick your system if you're not already booting coreboot. Expect to do an external flash initially.
This information should not be considered reliable in any way, shape or form
- GPIO57 - OUT - controls WLAN (rfkill pin on minipcie slot)
- GPIO54 - OUT - seems to control bluetooth
General Purpose Events layout
- GEVENT3 -> GPE3 - EC SCI
- GEVENT23 -> GPE23 - EC SMI
- GEVENT22 -> GPE22 - Lid
To ACPI or not to ACPI
The EC likes to start up in APM mode. In APM mode, it will generate an SMI whenever an external event occurs. To make it generate SCIs instead, and play nicely with ACPI, we need to tell it to go to ACPI mode.
The MMIO dilemma
The EC RAM, which contains the batterry/AC etc information is normally accessed by read commands on the EC index I/O ports (0x62 and 0x66). The EC will also respond to LPC memory read/write cycles in the address range 0xff000000 + 0x1000. In order for this to work, the chipset must pass MMIO accesses in this range to the LPC bridge, which in turn, must decode them to the LPC bus.
This can't work if there is something else using that address range, so any system with 16MiB is out of the question. Luckily, the 1035dx uses a 4 MiB chip, so that's a non-issue. As a bonus, the LPC bridge can map a 4 KiB MMIO window on the LPC bus (or two, I can't remember).
The EC RAM is at an offset of 0x800 from the MMIO base address. The current compal/ene932 ACPI implementation does not handle MMIO. This should be easily fixable with some preprocessor love.