Developer Manual/Memory map
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Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This page contains the description of various memory areas important for coreboot development.
Physical memory properties
All memory below 1 MB has special rules attached to it. Due to legacy reasons, you can't allocate memory freely in that area without taking care.
- 0x00000 - 0x9FFFF: Low 640kB. Should not be clobbered on S3 suspend/resume (exceptions?)
- 0xA0000 - 0xAFFFF: VGA graphics memory.
- 0xB0000 - 0xB7FFF: Old monochrome graphics text mode memory. May not apply for recent cards.
- 0xB8000 - 0xBFFFF: VGA text mode memory.
- 0xFEC0_0000 may be fixed location IO APIC. Other possible locations are 0xFECX_YZ00 (not that 0xFEC cannot be changed)
- 0xFEEx_xxxx are internal APIC cycles for IRQ (MSI)
- FEC0_0000 - FEC7_FFFF VIA APIC in SB (fixed)
- FEC8_0000 - FECB_FFFF -VIA VPXII APIC
- FED4_4000 - FED4_FFFF trusted platform module MEM decode (fixed)
- 0x00000200: Location of stage2 in v3
- 0xFEC00000: DEVICE_MEM_HIGH. The area between DEVICE_MEM_HIGH and 0xFFFFFFFF (4 GB) will be avoided by the resource allocator.