EHCI Debug Port
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Serial ports have been the primary means of early debugging of new LinuxBIOS ports. New hardware doesn't always have a serial port and another method for early debugging is needed.
What is this debug port and why is it special?
The EHCI Debug Port is an optional capability of EHCI controllers. All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.
Debug Class Device
While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.
Considerations in LinuxBIOS
We'll use Mode 1 since a full USB stack and EHCI driver isn't running when we're using the debug port. We get early two-way communication from PCI memory write accesses. printf() should transmit also to the debug port on any (all?) EHCI controllers sporting the capability. Linux already supports this and we could probably copy code or headers from the kernel.
The Debug Port is optional, please check if EHCI controllers near you support it:
# lspci -vs $(lspci|grep EHCI|cut -f1 -d' ') 00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI]) Subsystem: IBM Unknown device 0566 Flags: bus master, medium devsel, latency 0, IRQ 5 Memory at b0000000 (32-bit, non-prefetchable) [size=1K] Capabilities:  Power Management version 2 Capabilities:  Debug port
Look for the last line. If your controller isn't listed below, please add it, or send an email to the Mailinglist if you don't have a wiki account yet and want one, or want us to add your controller to this page.
- 8086:24dd Intel ICH5
- 8086:265c Intel ICH6
The Debug Port is described in Appendix C.
- Debug Class functional spec http://developer.intel.com/technology/usb/download/DebugDeviceSpec_R090.pdf
This is what has to be connected to the EHCI controller.