The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
You probably came here trying to find a small (minutes to hours) and easy task where you can get your hands dirty and get results immediately.
If you're a coreboot or flashrom newbie, this page is for you.
The flashrom tool can read/write coreboot/BIOS images from/to flash chips.
Add timing info to flash chip definitions
Go through the list of flash chips in flashchips.c inside the flashrom source. For each chip (except SPI chips), read through the data sheets and add a comment to the flash chip definition which contains the timing information in microseconds(!) for the probe sequence.
This will make probing a lot more reliable.
Every annotated chip helps.
Add the bus type to flash chip definitions
Go through the list of flash chips in flashchips.c inside the flashrom source. Look for chip definitions which have .bustype = CHIP_BUSTYPE_NONSPI and look at their data sheets. Read the data sheets and try to figure out the flash bus they use (Parallel/LPC/FWH/SPI). Change the bustype field to CHIP_BUSTYPE_PARALLEL etc. and post a patch to the list.
This will make probing faster and more reliable.
Even a single updated chip helps.
Flashrom#Communication_bus_protocol has a writeup on how to figure out the bus type.
Add new flash chip definitions
We have a few dozen chip IDs listed in flash.h, but not in flashchips.c. Find them, dig up the data sheets and add chip definitions for them to flashchips.c. You can use similar flash chips as a guideline.
This will reduce the number of undetected chips.
Every added chip broadens flashrom support.
If you have a desktop (no laptops/notebooks/netbooks), please run
and check if it finds your flash chip. If it does and any of the operations are listed as unsupported, we'd like to hear about it. If your flash chip is not found, we'd like to hear about it as well.
In both cases, please send the output of
I'll skip explaining what coreboot is. The whole wiki is about this topic and I can't summarize it in one sentence.
The workhorse version of coreboot. Lots of supported boards, but difficult to work with.
AMD 740G information gathering
(This project description is not finished yet)
If you have a board with AMD 740G chipset, please run (as root)
flashrom -V lspci -nnvvvxxxx superiotool -edV dmidecode
and mail the output to the coreboot mailing list together with the exact model number/name of your board.
This helps us evaluate which boards are good targets for coreboot.
Use CBFS wherever possible
- src/cpu/amd/model_lx/vsmsetup.c is a very good candidate. The VSM blobs should be loaded from CBFS.
The next generation version of coreboot. Few supported boards, still in the design testing phase, easy to work with.
TODO: Add easy tasks here.
coreboot can use a number of different payloads.
Add/test new supported payloads
- Test syslinux (probably requires SeaBIOS in addition, needs to be checked).
- Port GPXE to "native" coreboot (it works fine together with SeaBIOS though).