The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.
The Nokia IP330 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. There is as far as I known no CD support in the orginal BIOS.
The System has no VGA, all console activity must be done through a serial console. At the front the following can be found;
- Power LED
- Fault LED
- 2 Serial interfaces COM1 and COM2
- 3 Ethernet RJ45 sockets
- Reset button
- 1 Compact PCI slot
At the back the following can be found;
- EURO Power connector
- Power switch
- Three FANs for system unit cooling
- One FAN for CPU cooling
The current development status is; No coreboot running yet
|L1 cache enabled||WIP|
|L2 cache enabled||WIP|
|L3 cache enabled||N/A|
|Multiple CPU support||N/A|
|Dual channel support||N/A|
|On-board IDE 3.5"||OK||One IDE connector on-board|
|On-board IDE 2.5"||N/A|
|On-board Ethernet||WIP||Three intel SB82558B controllers.|
|On-board Smartcard reader||N/A|
|On-board SD card reader||N/A|
|ISA add-on cards||N/A|
|Audio/Modem-Riser (AMR/CNR) cards||N/A|
|PCI add-on cards||WIP|
|Mini-PCI add-on cards||N/A|
|Mini-PCI-Express add-on cards||Unknown|
|PCI-X add-on cards||N/A|
|AGP graphics cards||N/A|
|PCI Express x1 add-on cards||N/A|
|PCI Express x2 add-on cards||N/A|
|PCI Express x4 add-on cards||N/A|
|PCI Express x8 add-on cards||N/A|
|PCI Express x16 add-on cards||N/A|
|PCI Express x32 add-on cards||N/A|
|HTX add-on cards||N/A|
|Legacy / Super I/O|
|Serial port 1 (COM1)||OK|
|Serial port 2 (COM2)||OK|
|Sensors / fan control||WIP|
|CPU frequency scaling||N/A|
|Other powersaving features||N/A|
|ACPI||No||There's no ACPI implementation for this board, but it's on our TODO list.|
|Nonstandard LEDs||WIP||Special-purpose LED available on the board, Fault is controlled by the superio?|
|High precision event timers (HPET)||N/A|
|Random number generator (RNG)||N/A|
|Wake on modem ring||N/A|
|Wake on LAN||N/A|
|Wake on keyboard||N/A|
|Wake on mouse||N/A|
|Flashrom||WIP||Supported flashrom revision will be higher than 1257.|
On board of the IP530 can be found the following:
- CPU: Socket 7, AMD K6 II at 266 MHz normally,
- Some later models of the IP330 had a K6 II at 500 or 550 MHz. Special cooling shroud needed on those.
- I430TX northbridge.
- 82371 southbridge.
- intel 21150 PCI to PCI bridge.
- 28F200, 256 Kbyte flashrom.
- SMSC FDC37B932QF superio with 1024 bits SPI eeprom attached.
- LM72 temp controller.
- 3 intel 82558B ethernet controllers.
- 2 SD-RAM sockets.
- 64 Mb SDRAM by default. Definitely takes a 256 Mb PC133 fine, and rumoured to take a maximum of 512 Mb SDRAM.
- On early models there is one SDRAM slot, and solder pads for a second. Later models have both slots.
Below the description is given for the following;
- For the connectors on the mainboard of the Nokia IP330, due missing documentation of the manufacturer.
- To create a flash option board on the J-DEBUG connector.
- The layout of the SPI eeprom behind the SuperIO.
- J1 Backplane CPU fan
- J2 Backplane system fan
- J3 Backplane system fan
- J4 Backplane system fan
- J5 CPU fan (not used)
- J9 IDE connector
- J10 The Floppy connector
- J15 Serial port connector (ML10), COM2
- J16 Phone connector (behind front)
- J17 Ethernet RJ45 connector eth s3
- J18 Ethernet RJ45 connector eth s4
- J19 Ethernet RJ45 connector eth s5
- 1-2 = short reset CMOS ?
- JP2 (besides CPU, not soldered in)
- 1-2 = P or E mode
- 2-3 = All BLK locked (default)
- 1-2 = B.B. Unlocked
- 2-3 = B.B locked (default)
- 1-6 B.B. Locked (default)
- 2-5 B.B. Unlocked
- 3-4 B.B. DPD Locked
- JP11-JP13 Serial port COM2
- JP12-JP14 Internal modem
- P1 option power connector
- P2 IDE power connector
- P3 Serial port connector (DB9), COM1
- P6 Power connector
EEPROM behide the SuperIO
|0x00-0x05||6 bytes||IP530\x00||Product name|
|0x24-0x29||6 bytes||-||Board number, sticker close to the PIII cpu|
|0x2A-0x37||14 bytes||-||Mfg. P/n (on the bottom side of the unit), filled out with spaces|
|0x3E-0x3F||2 bytes||0xYY,0x00||Mfg. rev. (on the bottom side of the unit), 0xYY = is the revision letter, where A = 0x41, B = 0x42|
|0x52-0x5D||12 bytes||-||Serial number (on the bottom side of the unit)|
|0x7E-0x7F||2 bytes||0xFF,0xFF||Unknown, probably the checksum value, but not used therefore filled 0xFFFF|
On coreboot startup the eeprom is read, to determine if its a IP330, otherwise it get signaled. And the revision of the hardware. When its reads an unknown (at that time) herdware revision,
Be aware when accessing the data the addresses above are byte address, they need to be converted in word addresses.
The eeprom can be read through the LDN RTC of the superio.