The following are some ideas that have come up in the community. Some are more or less suitable for GSoC and prospective students' application should expand on some ideas and pair back others.
- 1 Linux Firmware Kit, BITS
- 2 Infrastructure for automatic code checking
- 3 coreboot test suite
- 4 coreboot cheap testing rig
- 5 coreboot mainboard test result reporting
- 6 coreboot ports for mainboards
- 7 Tianocore as payload
- 8 coreboot ACPI 4.0 and S3 power management support
- 9 coreboot port to ARM SOC's with PCIe
- 10 coreboot panic room
- 11 Board config infrastructure
- 12 Refactor AMD code
- 13 AMD VSA
Linux Firmware Kit, BITS
There are various test suites for firmware aspects, esp. those that interacts with the operating systems. Unfortunately, some of these projects are dead, some seem to be forked and developed semi-publically, and having all that stuff in lots of different places is a big hassle.
The goal of this project is to pick up the pieces, and create a single tool (most likely a bootable CD/USB drive image) that can be booted on vendor BIOS (for the Red Hat and Canonical developers that work on these) as well as coreboot (preferably seabios and FILO to improve testability - is an issue created/fixed by coreboot or seabios?). This can then be improved in various ways.
There's also intel-gpu-tools that might have some useful tests (at least for intel-boards): http://article.gmane.org/gmane.comp.video.dri.devel/63948
When applying for this task, please state in your proposal what you think might be worthy extensions to the existing tests.
Required knowledge for this task: Minimal coreboot and firmware experience, but you should have some idea of the boot process of a Linux system (as these test suites are mostly Linux based). GSoC probably won't provide enough time to learn all that (Linux boot process, firmware interfaces such as ACPI) and still develop the tools in some useful way.
- Supported Motherboards
Infrastructure for automatic code checking
We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:
- Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
- Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
- Use LLVM's static code checking facilities, report regressions.
- LLVM tools: Clang static analyser, SSA assertion checker, http://klee.llvm.org/
- Lint tools: Splint
- Semantic Tester: https://code.google.com/p/c-semantics/
coreboot test suite
Create a test suite to gather and report coreboot mainboard and payload settings. This project may leverage libpayload, coreinfo, memtest86, BITS, and other tools like benchmarks for CPU and RAM performance. Konstantin Aladyshev reported according to the benchmark STREAM, RAM access on his system with coreboot is four times slower than with the proprietary vendor BIOS. Such issues should be easily spotted with the test suite.
The suite should gather result and report them at summary and detailed levels. The goal is to help coreboot developers identify problems and to test coreboot features. This project should work closely with the testing rig and test reporting projects. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.
coreboot cheap testing rig
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:
The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as X10, it's possible to drop the testing costs per board significantly.
- InSystemFlasher is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.
coreboot mainboard test result reporting
One of the biggest challenges in coreboot is support many systems in the same codebase. As systems age and coreboot continues to develop, the condition of mainboards becomes unknown. This project would define a coreboot test results reporting mechanism, gather data, and report passing and failing systems on a webpage. This project would work closely with the coreboot test suite project and/or the hardware test rig project. A good example of test results gathering and reporting is done by the Phoronix/Openbenchmark. The student should investigate other test and reporting solutions to leverage the best options for coreboot. It is important the the student considers how testing and reporting can be extended as features and tests are added in the future.
coreboot ports for mainboards
Identify potential mainboards to port based on the recently release cpu and chipset support. The goal would be to support publicly available platforms with a number of payloads and operating systems.
Tianocore as payload
What SeaBIOS is for PC-BIOS interfaces, Tianocore is for UEFI - in fact, it's the reference implementation that most commercial UEFIs are built on. While coreboot favors other design goals than UEFI, it's really useful to support this standard that's being pushed on the market, just like SeaBIOS really helped coreboot by providing a BIOS "frontend".
There's already some code, but there's still much room for improvement: A graphics driver that uses a preinitialized (by coreboot) framebuffer. A CBFS driver so Tiano can access coreboot flash storage. Based on that, a flash driver (maybe adapted from flashrom) to implement non-volatile variable storage by writing to flash.
Possible tasks depend a lot on existing knowledge of the candidate. Few of the tasks are large enough to fill the entire GSoC time frame with one of them. Feel free to discuss with us on IRC what a suitable target could be for you.
coreboot ACPI 4.0 and S3 power management support
coreboot has support for ACPI tables and S3 support for some platforms, but it is very mainboard specific and moslty based on ACPI 2.0. Create a generic solution for ACPI 4.0 table generation and S3 support.
coreboot port to ARM SOC's with PCIe
ARM SOC's with PCIe are available. These systems can take advantage of coreboot's strength in properly configuring PCI devices, fast boot time and payload support.
Note that coreboot has in the past supported three different CPUs (x86, Alpha, PPC), so the structure is there for adding in a new processor family. We will need to find the right platform to do the work, but I (Ron) can provide a board and JTAG debugger if needed.
There was an ARM project started in 2011.
coreboot panic room
Create a safe boot solution for coreboot to easily and cheaply recover the system.
The basic idea is that the system flash image always contains executable for SerialICE. Instead of loading a coreboot romstage, firmware can boot to SerialICE based on some GPIO state, a keypress sequence or a logged failure on earlier boots. It is possible to integrate this into the coreboot build tree as a bootblock option, in the same spot as the fallback/normal switch and the simple loader.
Having this capability opens up new possibilities:
During the lifetime of a mainboard, new requirements for ACPI hacks and CPU microcodes introduce the need to update boot firmware at customer site. The firmware shall have recovery path against any failures during the firmware update process. The most straight-forward solution is to do intelligent allocation of files in the CBFS such that files critical to the recovery are located on write-protected pages. The recovery path shall require only an USB mass-storage with compatible filesystem (ext2, fat32).
The ability to dual-boot reduces the amount of tools required to reverse-engineer proprietary BIOS on ports for new mainboards. It is increasingly common that the flash chips are a) not socketed or b) physically hard to access (laptops). Even if chipset support existed already for a board, there are a lot of configuration registers for PCI-e links and GPIO signals that are difficult to get right by code disassembly only. With panic room implementation there would be no need to use external programmers or flashchip hot-swap method to alternate between SerialICE (for proprietary BIOS) and coreboot romstage boots.
SerialICE requires minimal hardware resources and does not require installed RAM or display hardware. It could be used as the first power-on environment after mainboard PCB verification and assembly to verify integrated components enumerate correctly. At the end of this first power-on, actual board firmware can be programmed without the need for external programmers and SOIC-8 clips, as the SPI controller embedded in the chipset can be used instead. As setting up EHCI debug port console is fairly simple across different chipsets, it can be used to print detailed diagnostics instead of POST codes on LPC bus.
GSoC 2011 project  was able to:
- Link flashrom with libpayload and flash from USB drive in a pre-OS environment.
- Optimise flashrom memory usage to flash in pre-ram/cache-as-ram environment.
- Build SerialICE boot ROM inside the coreboot tree and share some of the PnP/SuperIO source code.
- Demonstrate booting alternative payload on keypress.
There are remaining open tasks to:
- Bring the GSoC 2011 patches up-to-date with current flashrom and libpayload trees.
- Create generic solution to jump to recovery mode using input from GPIOs and/or use of power-button override.
- Use SMBus/SMLink to send POST failure codes over ethernet using integrated network controllers.
- After panic(), dump RAM contents before they are overwritten.
Board config infrastructure
Design data structures that host information about the board layout so coreboot can better initialize components and generate all kinds of tables (mptable, pirq, acpi, ...) from that dynamically (at build or runtime, as appropriate). Adapt boards to use that instead of the current hardcodes.
Refactor AMD code
AMD K8 and AMD Fam10 are different enough to have their own code. This is unfortunate, as you have to decide which CPU type you use in a given mainboard. Refactor AMD code so a single image can support both chip types on a given board. Also move tables from get_bus_conf and the like to the device tree or kconfig options (or runtime detection), as appropriate.
Alternatively, figure out a way how to build them in parallel and have coreboot select the right one on runtime.
Get the source code of AMD's VSA compiled and working with an open source toolchain. Integrate the it into the current build system.