User contributions for Uwe
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24 June 2009
- 14:1014:10, 24 June 2009 diff hist +604 N Serial console Created page with '== coreboot == == FILO == == GRUB == In your '''boot/grub/menu.lst''' add the following: serial '''--unit=0''' --speed='''115200''' terminal --timeout=15 serial console Ch…'
- 14:0514:05, 24 June 2009 diff hist −44 m Creating Valid IRQ Tables No edit summary current
- 14:0114:01, 24 June 2009 diff hist +4 m IRC No edit summary
- 13:3713:37, 24 June 2009 diff hist −592 m Developer Manual No edit summary
- 13:3513:35, 24 June 2009 diff hist +603 m Developer Manual/Tools No edit summary
- 13:3413:34, 24 June 2009 diff hist −2,771 m Developer Manual →Serial output and the Super I/O
- 13:3413:34, 24 June 2009 diff hist +2,805 Nm Developer Manual/Super IO Created page with 'The Super I/O is a chip found on most of today's mainboards which is — among other things — responsible for the serial ports of the mainboard …'
- 13:2913:29, 24 June 2009 diff hist −2,200 m Developer Manual →RAM init
- 13:2913:29, 24 June 2009 diff hist +2,234 Nm Developer Manual/RAM init Created page with 'One of the most important tasks of coreboot is to initialize your system RAM. === SDRAM === There are a number of steps you have to perform to properly initialize SDRAM. This d…'
- 13:2813:28, 24 June 2009 diff hist +17 m Developer Manual →Memory map
- 13:2813:28, 24 June 2009 diff hist 0 m Developer Manual/Memory map moved Memory map to Developer Manual/Memory map: Belongs into the developer manual.
- 12:5312:53, 24 June 2009 diff hist −9,574 m Developer Manual Move
- 12:5112:51, 24 June 2009 diff hist +9,691 N Developer Manual/Tools Move
- 01:2001:20, 24 June 2009 diff hist +65 m Board:soyo/sy-6ba-plus-iii No edit summary
- 00:2500:25, 24 June 2009 diff hist +199 m Board:soyo/sy-6ba-plus-iii No edit summary
- 00:2000:20, 24 June 2009 diff hist −9 m File:Soyo sy-6ba plus iii.jpg No edit summary current
- 00:2000:20, 24 June 2009 diff hist +125 N File:Soyo sy-6ba plus iii.jpg Soyo SY-6BA+ III photo. Author: [mailto:ziltro@ziltro.com Andrew Morgan] License: {{CC-BY-SA 3.0}}
- 00:1300:13, 24 June 2009 diff hist +2,393 N Board:soyo/sy-6ba-plus-iii Created page with '== Status == {{Status| |CPU_status = OK |CPU_L1_status = OK |CPU_L1_comments = CPU: L1 I cache: 16K, L1 D cache: 16K |CPU_L2_status = WIP |CPU_L2_comments = L2 cache is not bei…'
23 June 2009
- 23:4023:40, 23 June 2009 diff hist +462 Infrastructure Projects →More ideas: Common payload location.
- 20:4320:43, 23 June 2009 diff hist +82 m Supported Chipsets and Devices →Devices supported in coreboot v2