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- External and SATA port 4 is not detected. This is due to bug in Coreboot code with regards of Combined mode handling. * only channel0 populated (DDR1 and DDR3 slot, DDR1 is closest to CPU) - strange UMA artefacts ...3 KB (552 words) - 23:20, 18 January 2014
- ...may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS) * S3 (Suspend to RAM) ...9 KB (1,542 words) - 13:30, 19 May 2018
- ...the VGA bios and concatenate it with the coreboot image, before burning it to your ROM. See below for details. coreboot requires a [[Payloads|payload]] to boot an operating system. ...10 KB (1,428 words) - 03:56, 19 January 2014
- referred to as CBFS). CBFS is a scheme for managing independent chunks /---------------\ <-- Start of ROM ...29 KB (4,567 words) - 01:31, 1 August 2017
- I am currently investigating only and plan to start porting at the Prague meeting 2014. Even worse, the top ~200 kB (0x2FFFF bytes) are read-only due to Protected Region 0. ...5 KB (642 words) - 06:36, 6 January 2017
- == HOWTO to find a way == * fetch and built these tools (you'll need to have at least '''libpci''' and '''pciutils''' installed for some of these): ...7 KB (1,169 words) - 16:11, 2 March 2020
- The FlexyICE connects to a computer via USB. It connects to the target via an LPC header. ...ongle_fpga/overview free software and full schematics] (scroll all the way to the bottom for download links, or click on the CVS: browse link near the to ...8 KB (1,391 words) - 06:11, 14 April 2015
- ...w coreboot can help with various security aspects of your system, compared to proprietary/closed-source boot firmware implementations(BIOS/EFI/UEFI). It ...nths before being available on non-free firmwares, if you are lucky enough to have them. ...9 KB (1,423 words) - 23:39, 2 January 2018
- This page describes how to use coreboot on the '''[http://de.kontron.com/products/boards+and+mezzanine ...the same size (and reasonably similar timing probably: The controller has to operate in Dual Channel mode for now). ...11 KB (1,525 words) - 23:22, 18 January 2014
- ...may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS) ...o causes the "Tablet Service" tsmservice.exe to hog one cpu core. It needs to be disabled.) ...7 KB (1,172 words) - 08:21, 23 April 2018
- The v3 resource allocator should be ported to v4. '''Status:''' Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources. ...8 KB (1,219 words) - 16:45, 17 August 2016
- Mainboards where the BIOS chip is soldered onto the board (i.e., not in a socket) are usuall ...oldering guru to do any of this, with a little practice everyone can learn to perform the procedure. ...11 KB (1,845 words) - 19:19, 22 January 2010
- == Things to know == ...e fields are used by [[payloads]] — for instance all the fields that start with '''boot_''' in the list above. [[FILO]] and [[Etherboot]] are two exam ...7 KB (1,059 words) - 20:48, 6 September 2015
- ...the information is about the Geode LX and CS5536 but may also be relevant to older versions of Geode. (Note that this does not cover the Geode NX). ..._13022%5E13060,00.html DB800 reference design], so that is a good place to start. ...10 KB (1,774 words) - 16:02, 26 May 2013
- ...they will be helpful to others, and the resulting work will be upstreamed to the main repository once it has been regression-tested in the context of Ch ...platform/dev-util/+/master/host/cros_bundle_firmware cros_bundle_firmware] to modify the image produced by the coreboot build system. For instance, the l ...19 KB (2,778 words) - 17:53, 19 March 2015
- To: Ronald G. Minnich currently using. This code, in northbridge/raminit.c, is an ugly hack to get ...9 KB (1,597 words) - 23:08, 5 April 2007
- * Succesfully booting to OS * AC status LED next to power jack (white = charged, amber = charging) ...8 KB (1,392 words) - 04:24, 30 January 2015
- Set the '''PMIO base address''' to some known address, and set up the desired ACPI IRQ (usually IRQ9; sometime ...or kernel ACPI implementation. This is the '''FACP''' table. You will need to create the '''fadt.c''' file and fill in the I/O port values plus IRQ: ...20 KB (3,294 words) - 02:26, 8 December 2017
- This HOWTO explains how to use coreboot on the M4A785T-M board. The main difference between the '''[ht |CPU_L1_comments = How to test? ...9 KB (1,387 words) - 18:59, 13 October 2016
- Disclaimer: This board is not widely sold any longer. However, refer to [[#F2A85_series_status|F2A85 series status]] for newer models. ASUS F2A85 P |CPU_comments = the board will start with an AMD A8-5500 ...9 KB (1,445 words) - 12:10, 2 May 2017