Search results

Jump to navigation Jump to search
  • |YES || Compatibility with TPM modules that fit ASUS TPM header. (Connected over | YES ...
    19 KB (3,122 words) - 16:54, 10 May 2018
  • aio_load="YES" kqemu_load="YES" ...
    7 KB (1,085 words) - 17:17, 29 May 2015
  • ...ould make use of it to create highly-customized payloads for Coreboot. And yes, we can have sl in our boot firmware! ...
    3 KB (554 words) - 15:47, 13 October 2017
  • fpu : yes fpu_exception : yes ...
    10 KB (1,462 words) - 23:21, 18 January 2014
  • ...hould not change. You can adjust the IRQs generated by changing PIRQA etc. Yes, it is fine if they all share 10 or 11 but it might be easier to debug if t ...36_early_setup(). The MSR name is PM Fail-Safe Delay and Enable (PM_FSD). (Yes, this could be made a Config.lb option) ...
    10 KB (1,774 words) - 16:02, 26 May 2013
  • fpu : yes fpu_exception : yes ...
    14 KB (2,140 words) - 23:21, 18 January 2014
  • ...API duplex=half firmware=rtl_nic/rtl8168d-2.fw latency=0 link=no multicast=yes port=MII speed=10Mbit/s ...=3.16.0-4-amd64 firmware=N/A ip=192.168.1.178 latency=0 link=yes multicast=yes wireless=IEEE 802.11bgn ...
    49 KB (5,467 words) - 01:09, 29 November 2015
  • Exit and when asked to generate a config file say yes. After, execute: ...
    9 KB (1,416 words) - 22:29, 26 September 2009
  • These are some copy/paste instructions that will fetch it and run it in qemu(yes, you should already have it installed): ...
    7 KB (1,238 words) - 11:08, 23 March 2009
  • ...ver=r8169 driverversion=2.3LK-NAPI duplex=half latency=0 link=no multicast=yes port=MII speed=10Mbit/s fpu : yes ...
    92 KB (9,722 words) - 02:31, 29 November 2015
  • bcdedit /store bcd /set {default} debug yes ...
    8 KB (1,244 words) - 13:47, 2 November 2013
  • $ flashrom -pinternal:laptop=force_I_want_a_brick,amd_imc_force=yes -w coreboot.rom ...
    8 KB (1,392 words) - 04:24, 30 January 2015
  • Yes, see [[IRC]]. And if yes, can they be modified? ...
    30 KB (4,955 words) - 18:41, 5 March 2018
  • ...unclear if the chipset actually has EHCI Debug Port functionality, and (if yes), whether the current coreboot code supports it properly (or whether it's j ...
    12 KB (1,850 words) - 20:18, 20 August 2017
  • you, and you've noticed that yes, it does do that, but the defaults it ...
    30 KB (4,904 words) - 06:53, 21 October 2017
View ( | next 20) (20 | 50 | 100 | 250 | 500)