Difference between revisions of "User:GNUtoo"

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* I did the port to the M4A785T-M (With a serial port)
+
== Wiki contributions ==
* I've a Lenovo X60 (With a serial port)
+
My contributions to this wiki are available under the following licenses:
* I've a Lenovo T60 (Without a Serial port)
+
* [https://creativecommons.org/licenses/by-sa/3.0/legalcode CC-BY-SA 3.0]
* I've an alix.1C (With a serial port)
+
* [https://creativecommons.org/licenses/by-sa/4.0/legalcode CC-BY-SA 4.0] or later
 +
* [https://www.gnu.org/licenses/fdl.txt GFDL 1.3] or later
  
== My TODO list ==
+
== Code contributions ==
=== T60 ===
+
In the [https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=Documentation/gerrit_guidelines.md;h=1833b0a8f0dc89001547c73457d113a4a56fbd31;hb=refs/heads/master#l31 gerrit guidelines] there the follwing line: "Don't modify other people's patches without their consent."
* Find out why it hang when the power supply is removed
+
 
 +
I consent to the modification of my patches by anybody. I work on specific things because no one wants to do what I want to do. Else I'd be happy if someone else did the work, so I could pick the next task in my huge TODO list.
  
== scripts to help getting rid of the vbios of the x60 ==
+
Interests:
=== Script 1: generate the io access for the coreboot driver ===
+
* 100% Free computers(Laptops, Desktops, Home Servers, routers).
* follow "Case study: new laptop (not complete, sorry)" in https://docs.google.com/document/d/1g8FMob25VZYxbWri2iFB8YiSL8gwF9vKJH3HGxr0xQU/edit?pli=1
+
* Security
* pacman -S plan9port
+
** Secure boot trough GRUB with full disk encryption (no /boot in clear)
* cp /opt/plan9/bin/ssam ./
+
** Protect against DMA and other attacks that have access to the x86 cpu's RAM.
* replace the following line in ./ssam:
+
* Making it possible for end user to be able to use coreboot/libreboot:
#!/usr/local/plan9/bin/rc
+
** Making it easy or scalable to install coreboot/libreboot.
by the following line:
+
** Making it usable.
#!/opt/plan9/bin/rc
+
* Making less risky to reflash, permitting users without an external programmer to easily reflash, and developers to develop anywhere without a huge setup consisting of another computer and the coreboot computer beeing worked on. I'm also interested in getting the cbmem logs written to flash to make debugging easier when no other computer is available(for instance while the developer is traveling to a conference).
* create the ssamfix file with:
 
  ,s/\[ *[0-9]+\..[0-9]+\]//g
 
  ,s/^ *//g
 
y/^[RWU]/s/^/M /g
 
  ,s/\nU/ ;;;UDELAY/g
 
  ,|uniq -c
 
  ,s/^ *//g
 
  ,s/(^[0-9]+) ([MRW])/\2 \1/g
 
  ,s/"/\\"/g
 
  ,s/^M ([0-9]+) *(\[.*)/{M, \1, "\2"},/g
 
  ,s/^M ([0-9]+) *(.*)/{M, \1, "\2"},/g
 
  ,s/:  */:/g
 
  ,s/...UDELAY *([0-9]+)/\1/g
 
  ,s/^([RW]) ([0-9]+) (.*):0x([0-9a-f]+)(.*)/{\1, \2, "", \3, 0x\4, \5},/g
 
* run the following commands:
 
. /etc/profile.d/plan9.sh
 
cat dmesg| ./ssam  -f ssamfix > foo.c
 
  
=== Script2: compare the io access that were too fast ===
+
== Howtos ==
* Replace {V,0,}, with {V,7,}, in src/mainboard/vendor/device/i915io.c
+
* [[/make boot software writable for recent Intel computers]]
* cat /dev/ttyUSB0 > accesses.txt
+
* [[/External GPU init without running the option rom]]
* Use that script against accesses.txt to find the guilty accesses:
 
#!/usr/bin/env python2
 
import sys,re
 
 
 
def main(args):
 
try:
 
f = open(args[1],'ro')
 
except:
 
print args[0], " <file>"
 
 
for line in f:
 
if re.match("0x[0-9]*: Got .*, expect .*",line):
 
line = line.replace('\r\n','').replace(", expect ",':').replace(": Got ",':')
 
split = line.split(':')
 
#print split
 
if split[1] != split[2]:
 
print line
 
if __name__ == '__main__':
 
main(sys.argv)
 
  
== How to get semantic IOs ==
+
= X60/I945 native GPU init History =
In i915tool:
+
The Lenovo X60 GPU init has been merged a long time ago.
* import your IOs in prettyregs.c
+
Since then it has been rewriten/improved a lot by other people (See git log for more details).
* compile prettyregs.c
+
Thanks to all that work it's now a proper driver.
* run prettyregs
 
  
== How to get rid of the vbios of the x60 [New Version] ==
+
So I've moved the X60 GPU init information in [[/X60_GPU_init|a subpage]]
WARNING: DO NOT ATTEMPT TO DO THAT WITHOUT A FLASH RECOVERY MECANISM
 
  
Apply the [http://review.coreboot.org/#/c/3277/ coreboot patches], and adapt them for your mainboard
+
= Personal oppinions =
 +
* [[/Microcode]]
 +
* [[/Yabel]]
  
Then configure coreboot with:
+
= For coreboot developers =
[*] Output verbose x86emu debug messages
+
This section is mainly usefull for finding informations for:
[ ]  Trace JMP/RETF
+
* Asking me to test some code (that's why I listed all my hardware).
[ ]  Trace all opcodes
+
* Find my work in progress code.
[ ]  Log Plug&Play accesses
+
* Find legacy code.
[ ]  Log Disk I/O
+
* Find what I'm interested in working on:
[ ]  Log PMM
+
** If you want to work on the same thing than me, you could contact me if you want so:
[ ]  Debug VESA BIOS Extensions
+
*** I could help if I have time.
  [ ]  Redirect INT10 output to console
+
*** I could test if I have time.
[ ]  Log intXX calls
+
*** I may have some pointers.
[ ]  Log special memory accesses
+
* HOWTO that documents how to do a native VGA init for the Lenovo x60:
[ ]  Log all memory accesses
+
** It probably applies to the Lenovo t60 that have an Intel GPU, with no or very minor modifications.
[*]  Log IO accesses
 
Build and flash coreboot.
 
  
git clone [https://code.google.com/r/gnutoo-i915tool-x60/source/list my fork of the i915tool] until the code is merged in the [https://code.google.com/p/i915tool/ official i915tool].
+
== My hardware ==
 +
=== Mainboard/Devices running coreboot ===
 +
{| class="wikitable"  border="1"
 +
! Device/Mainboard
 +
! Serial/output
 +
! flash recovery mecanism
 +
! What I worked on
 +
|-
 +
| Asrock E350M1
 +
|
 +
* cbmem -c
 +
* Serial
 +
| rowspan="3" |
 +
* External programmer
 +
* Swapping the flash chip
 +
|
 +
|-
 +
| Asus F2A85-M PRO
 +
|
 +
* cbmem -c
 +
| rowspan="2" |
 +
* I've been the main porter.
 +
* Usability improvements
 +
|-
 +
| Asus M4A785T-M
 +
|
 +
* cbmem -c
 +
* Serial
 +
|-
 +
| Lenovo X60
 +
| rowspan="4" |
 +
* cbmem -c
 +
* Serial on the dock
 +
* spkmodem
 +
* USB debug
 +
| rowspan="5" |
 +
* External programmer with pomona clip
 +
| rowspan="2" |
 +
* Native GPU init
 +
* Usability improvements.
 +
|-
 +
| Lenovo X60T
 +
|-
 +
| Lenovo T60
 +
|
 +
* Usability improvements.
 +
|-
 +
| Lenovo T400
 +
|
 +
|-
 +
| Lenovo X200
 +
|
 +
* cbmem -c
 +
|
 +
|-
 +
| PC Engines Alix 1.C
 +
|
 +
* Serial
 +
|
 +
* Hot swap with the LPC dongle|
 +
* Usability improvements.
 +
|-
 +
|}
  
Get the [http://www.coreboot.org/images/4/42/Dennis.tar.gz tarball] that contains the generated code, extract it.
+
=== Mainboard/Devices not running coreboot (yet?) ===
 +
If you need to have some tests done on the default boot firwmare, you should ask me as it is fast to do if I've the laptop nearby.
  
Also get the [http://www.coreboot.org/images/3/39/I915_reg.h.gz i915_regs.h.gz] file, decompress it and put it in final/
+
{| class="wikitable"  border="1"
 +
! Device/Mainboard
 +
! Reason
 +
|-
 +
| Lenovo Thinkpad X200T
 +
| I need to find a way to be able to easily, robustly, and safely reflash it:
 +
* If a SOIC8 SPI chips is soldered instead of the WSON8 one, the solder past must not affect the stability of the SOIC8 clip. That is probably the most adapted way for me.
 +
* Wires aren't ideal if they break easily.
 +
* Internal flashing can't be trusted for freedom/privacy/security: The hardware probably permits boot firmwares to  very easily mess up with the flash content while it's being read or written: The hardware can probably be programmed to emmit SMM interrupts when the flash chip is accessed, and once in SMM, modify the data. This is the case on i945 thinkpads, however I didn't check the X200T datasheet yet, hence the "probably".
 +
|-
 +
|}
  
Then go into i915tool and apply some patches for the x60 or redo them for your mainboard.
+
=== Debugging tools ===
 +
* External programmers :
 +
** Arduino duemillanove (serprog based)
 +
** Arduino uno (serprog based)
 +
** openmoko debug board (FTDI based)
 +
** bug20 (linux_spi)
 +
* A pomona clip
 +
* a null-modem serial cable and 2 USB<->Serial adapters
 +
* [[EHCI Gadget Debug|USB debug]] compatible devices:
 +
** a bug20 (omap3530)
 +
** a GTA04 A3 (DM370)
  
Run make:
+
==  My TODO list ==
$ cd i915tool
+
See also TODO of the respectives machines on their dedicated wiki page.
$ make
+
* Merge or abandon my old patches.
Then go into the x60 directory(or the directory of your device):
+
* I945, GM45, GS45 thinkpads: Have all hardware features working (feature parity with the default boot firmware):
$ cd x60
+
** IRDA
use picocom -b 115200 /dev/ttyUSB0 or stty to set the bauds of the Serial port.
+
** TPM
Then get logs:
+
** Testing: write tests for
$ cat /dev/ttyUSB0 | tee coreboot.log
+
*** suspend/resume
Then remove the binary symbols, dos2unix will help identifying where they are:
+
*** power consumption
$ dos2unix coreboot.log
+
*** heat
dos2unix: Binary symbol found at line 136332
+
* GM45: Merge ich9gen functionality in ifdtool or ifdfake
dos2unix: Skipping binary file coreboot.log
+
* GM45: Investigate internal flashing (Look if BIOS->Modded BIOS->Coreboot works and understand why)
Then do:
+
* I945: SeaBIOS: allow booting on SD cards.
$ dos2unix coreboot.log
+
* Port a logging mecanism from chromebooks to all devices in order to be able to retrive the log of the failed boot at the next reboot.
Then remove the lines before and after the log, the log looks like that:
+
* Document flash protections and vboot.
[0047229e]c000:51cb outl(0x80001014, 0x0cf8)
+
* Verify if all the microcodes were moved away from coreboot git.
[0047325f]c000:51d4 inw(0x0cfc) = 0x50a1
+
* (Alix 1.C: port the VSA to fasm)
Then run make and fix the errors:
+
* (GDB improvements: allow gdb earlier than ramstage)
$ make
+
* I945: Write a freedom/privacy/security review
Then copy to coreboot as it says.
+
* GM45: Write a freedom/privacy/security review
Then if necessary try to compact the source code a bit, here for me I have a really long list of:
+
* More recent Intel with me_cleaner: Write a freedom/privacy/security review
io_i915_write32(0xcffbe001,0x8001);
 
io_i915_write32(0xcffbe001,0x8005);
 
io_i915_write32(0xcffbe001,0x8009);
 
io_i915_write32(0xcffbe001,0x800d);
 
io_i915_write32(0xcffbe001,0x8011);
 
That can be replaced with:
 
int i = 0;
 
for (i=0x8001;i<0x3fffa;i+=4){
 
io_i915_write32(0xcffbe001,i);
 
}
 
  
Import the final code into the chromium fork of coreboot with my patches on top.
+
= Work in progress documentation =
 +
* [[/Blobs-rewrite]]
 +
* [[/Golden Finger Connector]]
 +
* [[/Hardware Comparison]]
 +
* [[/APU1 reflashing]]

Latest revision as of 12:40, 10 May 2018

Wiki contributions

My contributions to this wiki are available under the following licenses:

Code contributions

In the gerrit guidelines there the follwing line: "Don't modify other people's patches without their consent."

I consent to the modification of my patches by anybody. I work on specific things because no one wants to do what I want to do. Else I'd be happy if someone else did the work, so I could pick the next task in my huge TODO list.

Interests:

  • 100% Free computers(Laptops, Desktops, Home Servers, routers).
  • Security
    • Secure boot trough GRUB with full disk encryption (no /boot in clear)
    • Protect against DMA and other attacks that have access to the x86 cpu's RAM.
  • Making it possible for end user to be able to use coreboot/libreboot:
    • Making it easy or scalable to install coreboot/libreboot.
    • Making it usable.
  • Making less risky to reflash, permitting users without an external programmer to easily reflash, and developers to develop anywhere without a huge setup consisting of another computer and the coreboot computer beeing worked on. I'm also interested in getting the cbmem logs written to flash to make debugging easier when no other computer is available(for instance while the developer is traveling to a conference).

Howtos

X60/I945 native GPU init History

The Lenovo X60 GPU init has been merged a long time ago. Since then it has been rewriten/improved a lot by other people (See git log for more details). Thanks to all that work it's now a proper driver.

So I've moved the X60 GPU init information in a subpage

Personal oppinions

For coreboot developers

This section is mainly usefull for finding informations for:

  • Asking me to test some code (that's why I listed all my hardware).
  • Find my work in progress code.
  • Find legacy code.
  • Find what I'm interested in working on:
    • If you want to work on the same thing than me, you could contact me if you want so:
      • I could help if I have time.
      • I could test if I have time.
      • I may have some pointers.
  • HOWTO that documents how to do a native VGA init for the Lenovo x60:
    • It probably applies to the Lenovo t60 that have an Intel GPU, with no or very minor modifications.

My hardware

Mainboard/Devices running coreboot

Device/Mainboard Serial/output flash recovery mecanism What I worked on
Asrock E350M1
  • cbmem -c
  • Serial
  • External programmer
  • Swapping the flash chip
Asus F2A85-M PRO
  • cbmem -c
  • I've been the main porter.
  • Usability improvements
Asus M4A785T-M
  • cbmem -c
  • Serial
Lenovo X60
  • cbmem -c
  • Serial on the dock
  • spkmodem
  • USB debug
  • External programmer with pomona clip
  • Native GPU init
  • Usability improvements.
Lenovo X60T
Lenovo T60
  • Usability improvements.
Lenovo T400
Lenovo X200
  • cbmem -c
PC Engines Alix 1.C
  • Serial
  • Hot swap with the LPC dongle|
  • Usability improvements.

Mainboard/Devices not running coreboot (yet?)

If you need to have some tests done on the default boot firwmare, you should ask me as it is fast to do if I've the laptop nearby.

Device/Mainboard Reason
Lenovo Thinkpad X200T I need to find a way to be able to easily, robustly, and safely reflash it:
  • If a SOIC8 SPI chips is soldered instead of the WSON8 one, the solder past must not affect the stability of the SOIC8 clip. That is probably the most adapted way for me.
  • Wires aren't ideal if they break easily.
  • Internal flashing can't be trusted for freedom/privacy/security: The hardware probably permits boot firmwares to very easily mess up with the flash content while it's being read or written: The hardware can probably be programmed to emmit SMM interrupts when the flash chip is accessed, and once in SMM, modify the data. This is the case on i945 thinkpads, however I didn't check the X200T datasheet yet, hence the "probably".

Debugging tools

  • External programmers :
    • Arduino duemillanove (serprog based)
    • Arduino uno (serprog based)
    • openmoko debug board (FTDI based)
    • bug20 (linux_spi)
  • A pomona clip
  • a null-modem serial cable and 2 USB<->Serial adapters
  • USB debug compatible devices:
    • a bug20 (omap3530)
    • a GTA04 A3 (DM370)

My TODO list

See also TODO of the respectives machines on their dedicated wiki page.

  • Merge or abandon my old patches.
  • I945, GM45, GS45 thinkpads: Have all hardware features working (feature parity with the default boot firmware):
    • IRDA
    • TPM
    • Testing: write tests for
      • suspend/resume
      • power consumption
      • heat
  • GM45: Merge ich9gen functionality in ifdtool or ifdfake
  • GM45: Investigate internal flashing (Look if BIOS->Modded BIOS->Coreboot works and understand why)
  • I945: SeaBIOS: allow booting on SD cards.
  • Port a logging mecanism from chromebooks to all devices in order to be able to retrive the log of the failed boot at the next reboot.
  • Document flash protections and vboot.
  • Verify if all the microcodes were moved away from coreboot git.
  • (Alix 1.C: port the VSA to fasm)
  • (GDB improvements: allow gdb earlier than ramstage)
  • I945: Write a freedom/privacy/security review
  • GM45: Write a freedom/privacy/security review
  • More recent Intel with me_cleaner: Write a freedom/privacy/security review

Work in progress documentation