[coreboot-gerrit] New patch to review for coreboot: 9810e23 usbdebug: Fixes for LynxPoint LP [NOTFORMERGE]
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Sun Jun 16 08:45:10 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3477
-gerrit
commit 9810e235dec088e29398ea1ead87a0308991b4e1
Author: Aaron Durbin <adurbin at chromium.org>
Date: Sat Jun 15 01:37:09 2013 +0300
usbdebug: Fixes for LynxPoint LP [NOTFORMERGE]
WIP
Need to fix EHCI_BAR in case of two controllers.
Change-Id: I7fe0eed24a66cb5058b49ee3fc0350d91089ed7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/southbridge/intel/lynxpoint/Kconfig | 8 ++++++--
src/southbridge/intel/lynxpoint/early_usb.c | 6 +++++-
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index f79e963..34f5cfb 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -26,7 +26,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select IOAPIC
select HAVE_HARD_RESET
- select HAVE_USBDEBUG
+ select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
@@ -41,12 +41,16 @@ config INTEL_LYNXPOINT_LP
config EHCI_BAR
hex
- default 0xfef00000
+ default 0xe8000000
config EHCI_DEBUG_OFFSET
hex
default 0xa0
+config USBDEBUG_HCD_INDEX
+ int
+ default 1
+
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/lynxpoint/bootblock.c"
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index ebd5c2c..a05668f 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -24,8 +24,12 @@
#include <device/pci_def.h>
#include "pch.h"
+#if CONFIG_USBDEBUG
+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+#else
#define PCH_EHCI1_TEMP_BAR0 0xe8000000
-#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+#endif
+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
/*
* Setup USB controller MMIO BAR to prevent the
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