[coreboot-gerrit] Patch set updated for coreboot: f7c1cc6 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Thu Apr 10 15:55:54 CEST 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5481
-gerrit
commit f7c1cc65d1d99958c12d4b2f64a59f69f93ee1fb
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Thu Apr 10 19:12:28 2014 +1000
mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Keep under 80 colums and Doxygen'ify inline documentation somewhat.
Strip some whitespace bulk while here.
Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h | 2 +-
.../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 20 ++++----
.../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 2 +-
src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 5 +-
src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c | 34 ++++++--------
src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h | 54 +++++++++-------------
src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 53 +++++++++++----------
src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 14 ++----
src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 4 +-
9 files changed, 84 insertions(+), 104 deletions(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
index c4f4f70..98cff3b 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.h
@@ -70,4 +70,4 @@ AGESA_STATUS BiosHookBeforeExitSelfRefresh (UINT32 Func, UINT32 Data, VOID *Conf
/* PCIE slot reset control */
AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-#endif //_BIOS_CALLOUT_H_
+#endif /* _BIOS_CALLOUT_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
index d7413cd..f24d2c2 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c
@@ -24,22 +24,20 @@
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
-/*---------------------------------------------------------------------------------------*/
/**
- * OemCustomizeInitEarly
+ * OemCustomizeInitEarly
*
- * Description:
- * This stub function will call the host environment through the binary block
- * interface (call-out port) to provide a user hook opportunity
+ * Description:
+ * This stub function will call the host environment through the binary block
+ * interface (call-out port) to provide a user hook opportunity
*
- * Parameters:
- * @param[in] **PeiServices
- * @param[in] *InitEarly
+ * Parameters:
+ * @param[in] **PeiServices
+ * @param[in] *InitEarly
*
- * @retval VOID
+ * @retval VOID
*
- **/
-/*---------------------------------------------------------------------------------------*/
+ */
VOID
OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
index 47ed1a5..c355799 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h
@@ -68,4 +68,4 @@ OemCustomizeInitEarly (
IN OUT AMD_EARLY_PARAMS *InitEarly
);
-#endif //_PLATFORM_GNB_PCIE_COMPLEX_H
+#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
index e7772aa..a236090 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c
@@ -31,7 +31,6 @@
#define DUMP_ACPI_TABLES 0
#if DUMP_ACPI_TABLES == 1
-
static void dump_mem(u32 start, u32 end)
{
@@ -45,7 +44,7 @@ static void dump_mem(u32 start, u32 end)
}
print_debug("\n");
}
-#endif
+#endif /* DUMP_ACPI_TABLES */
extern const unsigned char AmlCode[];
@@ -313,7 +312,7 @@ unsigned long write_acpi_tables(unsigned long start)
printk(BIOS_DEBUG, "hest\n");
dump_mem(hest, ((void *)hest) + hest->header.length);
-#endif
+#endif /* DUMP_ACPI_TABLES */
printk(BIOS_INFO, "ACPI: done.\n");
return current;
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
index 1627f25..2944eae 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.c
@@ -17,11 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*-----------------------------------------------------------------------------
- * M O D U L E S U S E D
- *-----------------------------------------------------------------------------
+/**
+ * Modules Used
*/
-
#include "agesawrapper.h"
#include "BiosCallOuts.h"
#include "PlatformGnbPcieComplex.h"
@@ -39,12 +37,10 @@
#include <cpu/amd/agesa/s3_resume.h>
#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
-#define FILECODE UNASSIGNED_FILE_FILECODE
-
-/*------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *------------------------------------------------------------------------------
+/**
+ * @brief Definitions and Macros
*/
+#define FILECODE UNASSIGNED_FILE_FILECODE
#define MMCONF_ENABLE 1
@@ -58,24 +54,20 @@ VOID *AcpiWheaMce = NULL;
VOID *AcpiWheaCmc = NULL;
VOID *AcpiAlib = NULL;
-/*------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *------------------------------------------------------------------------------
+/**
+ * @brief Typedefs and Structures
*/
-/*------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *------------------------------------------------------------------------------
+/**
+ * @brief Prototypes of local functions
*/
-/*------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *------------------------------------------------------------------------------
+/**
+ * @brief Exported functions
*/
-/*------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *------------------------------------------------------------------------------
+/**
+ * @brief Local functions
*/
uint32_t agesawrapper_amdinitcpuio(void)
{
diff --git a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
index 6af5e5f..c1e49d7 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
+++ b/src/mainboard/jetway/nf81-t56n-lf/agesawrapper.h
@@ -17,62 +17,54 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
#ifndef _AGESAWRAPPER_H_
#define _AGESAWRAPPER_H_
+/**
+ * Modules Used
+ */
#include <stdint.h>
#include <vendorcode/amd/agesa/f14/AGESA.h>
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
+/**
+ * @brief Definitions and Macros
+ *
+ * Define AMD Ontario APU SSID/SVID
*/
-/* Define AMD Ontario APPU SSID/SVID */
#define AMD_APU_SVID 0x1022
#define AMD_APU_SSID 0x1234
#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
enum {
- PICK_DMI, /* DMI Interface */
- PICK_PSTATE, /* Acpi Pstate SSDT Table */
- PICK_SRAT, /* SRAT Table */
- PICK_SLIT, /* SLIT Table */
- PICK_WHEA_MCE, /* WHEA MCE table */
- PICK_WHEA_CMC, /* WHEA CMV table */
- PICK_ALIB, /* SACPI SSDT table with ALIB implementation */
+ PICK_DMI, /**< DMI Interface */
+ PICK_PSTATE, /**< Acpi Pstate SSDT Table */
+ PICK_SRAT, /**< SRAT Table */
+ PICK_SLIT, /**< SLIT Table */
+ PICK_WHEA_MCE, /**< WHEA MCE table */
+ PICK_WHEA_CMC, /**< WHEA CMV table */
+ PICK_ALIB, /**< SACPI SSDT table with ALIB implementation */
};
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
+/**
+ * @brief Typedefs and Structures
*/
-
typedef struct {
UINT32 CalloutName;
AGESA_STATUS (*CalloutPtr) (UINT32 Func, UINT32 Data, VOID* ConfigPtr);
} BIOS_CALLOUT_STRUCT;
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/**
+ * @brief Prototypes of local functions
*/
-/*----------------------------------------------------------------------------------------
- * E X P O R T E D F U N C T I O N S
- *----------------------------------------------------------------------------------------
+/**
+ * @brief Exported functions
*/
-/*---------------------------------------------------------------------------------------
- * L O C A L F U N C T I O N S
- *---------------------------------------------------------------------------------------
+/**
+ * @brief Local functions
*/
-
UINT32 agesawrapper_amdinitreset (void);
UINT32 agesawrapper_amdinitearly (void);
UINT32 agesawrapper_amdinitenv (void);
@@ -92,4 +84,4 @@ void *agesawrapper_getlateinitptr (int pick);
UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader);
-#endif
+#endif /* _AGESAWRAPPER_H_ */
diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
index 1491f29..c41d418 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c
@@ -30,18 +30,19 @@
#include <southbridge/amd/cimx/sb800/sb_cimx.h>
-/* Global variables for MB layouts and these will be shared by irqtable mptable
-* and acpi_tables busnum is default.
-*/
+/**
+ * Global variables for mainboard layouts. These are shared by irqtable,
+ * mptable and acpi_tables where busnum is default.
+ */
u8 bus_isa;
u8 bus_sb800[6];
u32 apicid_sb800;
-/*
-* Here you only need to set value in pci1234 for HT-IO that could be installed or not
-* You may need to preset pci1234 for HTIO board,
-* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-*/
+/**
+ * Here you only need to set value in pci1234 for HT-IO that could be
+ * installed or not. You may need to preset pci1234 for HTIO board,
+ * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ */
u32 pci1234x[] = {
0x0000ff0,
};
@@ -53,7 +54,7 @@ static u32 get_bus_conf_done = 0;
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
void get_bus_conf(void)
{
@@ -68,21 +69,23 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
-/*
- * This is the call to AmdInitLate. It is really in the wrong place, conceptually,
- * but functionally within the coreboot model, this is the best place to make the
- * call. The logically correct place to call AmdInitLate is after PCI scan is done,
- * after the decision about S3 resume is made, and before the system tables are
- * written into RAM. The routine that is responsible for writing the tables is
- * "write_tables", called near the end of "main". There is no platform
- * specific entry point between the S3 resume decision point and the call to
- * "write_tables", and the next platform specific entry points are the calls to
- * the ACPI table write functions. The first of ose would seem to be the right
- * place, but other table write functions, e.g. the PIRQ table write function, are
- * called before the ACPI tables are written. This routine is called at the beginning
- * of each of the write functions called prior to the ACPI write functions, so this
- * becomes the best place for this call.
+/**
+ * This is the call to AmdInitLate. It is really in the wrong place,
+ * conceptually, but functionally within the coreboot model, this is the best
+ * place to make the call. The logically correct place to call AmdInitLate is
+ * after PCI scan is done, after the decision about S3 resume is made, and
+ * before the system tables are written into RAM. The routine that is
+ * responsible for writing the tables is "write_tables", called near the end of
+ * "main". There is no platform specific entry point between the S3 resume
+ * decision point and the call to "write_tables", and the next platform
+ * specific entry points are the calls to the ACPI table write functions. The
+ * first of ose would seem to be the right place, but other table write
+ * functions, e.g. the PIRQ table write function, are called before the ACPI
+ * tables are written. This routine is called at the beginning of each of the
+ * write functions called prior to the ACPI write functions, so this becomes
+ * the best place for this call.
*/
+
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
status = agesawrapper_amdinitlate();
@@ -96,7 +99,7 @@ void get_bus_conf(void)
status = agesawrapper_amdinitlate();
if(status)
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
sbdn_sb800 = 0;
memset(bus_sb800, 0, sizeof(bus_sb800));
@@ -142,5 +145,5 @@ void get_bus_conf(void)
#if CONFIG_AMD_SB_CIMX
sb_Late_Post();
-#endif
+#endif /* CONFIG_AMD_SB_CIMX */
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
index b77c375..e842c73 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c
@@ -58,15 +58,17 @@ unsigned long write_pirq_routing_table(unsigned long addr)
u8 sum = 0;
int i;
-
- get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
+ /* Find out all bus num and apic that are share with:
+ * mptable.c and acpi_tables.c
+ */
+ get_bus_conf();
/* Align the table to be 16 byte aligned. */
addr += 15;
addr &= ~15;
- /* This table must be betweeen 0xf0000 & 0x100000 */
+ /* This table must be between 0xf0000 & 0x100000 */
printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr);
pirq = (void *)(addr);
@@ -90,19 +92,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
-
/* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
-
-
slot_num++;
-
-
pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++)
@@ -117,5 +114,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "write_pirq_routing_table done.\n");
return (unsigned long)pirq_info;
-
}
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index d5f2d03..1d82cb9 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -64,7 +64,7 @@ static void mainboard_enable(device_t dev)
*/
#if CONFIG_HAVE_ACPI_RESUME
acpi_slp_type = acpi_get_sleep_type();
-#endif
+#endif /* CONFIG_HAVE_ACPI_RESUME */
/* enable GPP CLK0 thru CLK3 (interleaved) */
/* disable GPP CLK4 thru SLT_GFX_CLK */
@@ -75,7 +75,7 @@ static void mainboard_enable(device_t dev)
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;
- /*
+ /**
* Initialize ASF registers to an arbitrary address because someone
* long ago set things up this way inside the SPD read code. The
* SPD read code has been made generic and moved out of the board
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