[coreboot-gerrit] New patch to review for coreboot: 0f2b94c fsp_baytrail: Update function disable code

[Martin Roth (gaumless@gmail.com)]

Martin Roth (gaumless at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7653

-gerrit

commit 0f2b94c57f4bbfd5b12f867b1c4b1fd9830c92b7
Author: Martin Roth <martin.roth at se-eng.com>
Date:   Fri Dec 5 09:24:53 2014 -0700

    fsp_baytrail: Update function disable code
    
    - The EDS has the function disable bit for eMMC incorrectly listed
    as 8.  Changing it back to the correct bit 11.
    - The FSP will disable functions that it is told are disabled, so
    coreboot code that disables the functions is redundant.  Removing it.
    
    Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82
    Signed-off-by: Martin Roth <martin.roth at se-eng.com>
---
 src/soc/intel/fsp_baytrail/baytrail/pmc.h |  4 +--
 src/soc/intel/fsp_baytrail/southcluster.c | 48 -------------------------------
 2 files changed, 1 insertion(+), 51 deletions(-)

diff --git a/src/soc/intel/fsp_baytrail/baytrail/pmc.h b/src/soc/intel/fsp_baytrail/baytrail/pmc.h
index ee15dd9..df6355a 100644
--- a/src/soc/intel/fsp_baytrail/baytrail/pmc.h
+++ b/src/soc/intel/fsp_baytrail/baytrail/pmc.h
@@ -83,11 +83,9 @@
 #	define HSUART1_DIS	(1 <<  3)
 #	define HSUART2_DIS	(1 <<  4)
 #	define SPI_DIS		(1 <<  5)
-#	define MMC45_DIS	(1 <<  8)
-#	define EMMC_DIS		(1 <<  8)
 #	define SDIO_DIS		(1 <<  9)
 #	define SD_DIS		(1 << 10)
-#	define MIPI_DIS		(1 << 11)
+#	define MMC_DIS		(1 << 11)
 #	define HDA_DIS		(1 << 12)
 #	define LPE_DIS		(1 << 13)
 #	define OTG_DIS		(1 << 14)
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index 2216902..d87935b 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -424,44 +424,10 @@ static void sc_disable_devfn(device_t dev)
 		fd2_mask |= name_ ## _DIS
 
 	switch (dev->path.pci.devfn) {
-	SET_DIS_MASK(MIPI);
-		break;
-	SET_DIS_MASK(EMMC);
-		break;
-	SET_DIS_MASK(SDIO);
-		break;
-	SET_DIS_MASK(SD);
-		break;
-	SET_DIS_MASK(SATA);
-		break;
-	SET_DIS_MASK(XHCI);
-		/* Disable super speed PHY when XHCI is not available. */
-		fd2_mask |= USH_SS_PHY_DIS;
-		break;
 	SET_DIS_MASK(LPE);
 		break;
-	SET_DIS_MASK(MMC45);
-		break;
-	SET_DIS_MASK(SIO_DMA1);
-		break;
-	SET_DIS_MASK(I2C1);
-		break;
-	SET_DIS_MASK(I2C2);
-		break;
-	SET_DIS_MASK(I2C3);
-		break;
-	SET_DIS_MASK(I2C4);
-		break;
-	SET_DIS_MASK(I2C5);
-		break;
-	SET_DIS_MASK(I2C6);
-		break;
-	SET_DIS_MASK(I2C7);
-		break;
 	SET_DIS_MASK(TXE);
 		break;
-	SET_DIS_MASK(HDA);
-		break;
 	SET_DIS_MASK(PCIE_PORT1);
 		break;
 	SET_DIS_MASK(PCIE_PORT2);
@@ -470,20 +436,6 @@ static void sc_disable_devfn(device_t dev)
 		break;
 	SET_DIS_MASK(PCIE_PORT4);
 		break;
-	SET_DIS_MASK(EHCI);
-		break;
-	SET_DIS_MASK(SIO_DMA2);
-		break;
-	SET_DIS_MASK(PWM1);
-		break;
-	SET_DIS_MASK(PWM2);
-		break;
-	SET_DIS_MASK(HSUART1);
-		break;
-	SET_DIS_MASK(HSUART2);
-		break;
-	SET_DIS_MASK(SPI);
-		break;
 	SET_DIS_MASK2(SMBUS);
 		break;
 	SET_DIS_MASK(OTG);