[coreboot-gerrit] New patch to review for coreboot: 3f86b03 baytrail: don't allow PCIE wake ups
Aaron Durbin (adurbin@google.com)
gerrit at coreboot.org
Tue Jan 28 03:56:42 CET 2014
Aaron Durbin (adurbin at google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4972
-gerrit
commit 3f86b0347a479500596d78772ec9d5183edc304f
Author: Aaron Durbin <adurbin at chromium.org>
Date: Thu Nov 14 11:06:17 2013 -0600
baytrail: don't allow PCIE wake ups
The PCIe subsystem was constantly waking up boards from
S3 and S5. Completely disable PCIe wake ups. It can be made
mainboard-configurable later if needed.
BUG=chrome-os-partner:24004
BRANCH=None
TEST=Both S3 and EC RW->RW update (trip through S5) don't
cause wakeups.
Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176791
Reviewed-by: Shawn Nematbakhsh <shawnn at chromium.org>
---
src/soc/intel/baytrail/smm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c
index c654c85..e10c70b 100644
--- a/src/soc/intel/baytrail/smm.c
+++ b/src/soc/intel/baytrail/smm.c
@@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
- /* Configure events */
- enable_pm1(PWRBTN_EN | GBL_EN);
+ /* Configure events Disable pcie wake. */
+ enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS);
disable_gpe(PME_B0_EN);
/* Set up the GPIO route. */
More information about the coreboot-gerrit
mailing list