[coreboot-gerrit] Patch set updated for coreboot: 50e8544 NOTFORMERGE: fix reset.c
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sun Oct 26 02:34:02 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7196
-gerrit
commit 50e8544bc6a5b9da78787f42104bdb14a3c93ef8
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Sun Oct 26 10:36:02 2014 +1100
NOTFORMERGE: fix reset.c
Change-Id: I1a1412a1ee4125dcf1f01dc1f2ec6fd43b5d3c1f
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/southbridge/amd/amd8111/reset.c | 14 ++++++--------
src/southbridge/broadcom/bcm5785/reset.c | 6 ++----
src/southbridge/nvidia/ck804/reset.c | 6 ++----
src/southbridge/nvidia/mcp55/reset.c | 6 ++----
src/southbridge/sis/sis966/reset.c | 6 ++----
5 files changed, 14 insertions(+), 24 deletions(-)
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index c96e898..8824550 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -10,9 +10,7 @@
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
-typedef unsigned device_t;
-
-static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -20,7 +18,7 @@ static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
outb(value, 0xCFC + (addr & 3));
}
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -28,7 +26,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -37,9 +35,9 @@ static unsigned pci_read_config32(device_t dev, unsigned where)
}
#define PCI_DEV_INVALID (0xffffffffU)
-static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
+static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
{
- device_t dev, last;
+ pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <= last; dev += PCI_DEV(0,0,1)) {
@@ -57,7 +55,7 @@ static device_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
void hard_reset(void)
{
- device_t dev;
+ pci_devfn_t dev;
unsigned bus;
unsigned node = 0;
unsigned link = get_sblk();
diff --git a/src/southbridge/broadcom/bcm5785/reset.c b/src/southbridge/broadcom/bcm5785/reset.c
index 51ba6ec..b34cc86 100644
--- a/src/southbridge/broadcom/bcm5785/reset.c
+++ b/src/southbridge/broadcom/bcm5785/reset.c
@@ -26,9 +26,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
diff --git a/src/southbridge/nvidia/ck804/reset.c b/src/southbridge/nvidia/ck804/reset.c
index a241966..53c0c40 100644
--- a/src/southbridge/nvidia/ck804/reset.c
+++ b/src/southbridge/nvidia/ck804/reset.c
@@ -26,9 +26,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev >> 4) | where;
@@ -36,7 +34,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev >> 4) | where;
diff --git a/src/southbridge/nvidia/mcp55/reset.c b/src/southbridge/nvidia/mcp55/reset.c
index 0ec926f..520d836 100644
--- a/src/southbridge/nvidia/mcp55/reset.c
+++ b/src/southbridge/nvidia/mcp55/reset.c
@@ -29,9 +29,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
diff --git a/src/southbridge/sis/sis966/reset.c b/src/southbridge/sis/sis966/reset.c
index 0ec926f..520d836 100644
--- a/src/southbridge/sis/sis966/reset.c
+++ b/src/southbridge/sis/sis966/reset.c
@@ -29,9 +29,7 @@
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x7) << 12))
-typedef unsigned device_t;
-
-static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
@@ -39,7 +37,7 @@ static void pci_write_config32(device_t dev, unsigned where, unsigned value)
outl(value, 0xCFC);
}
-static unsigned pci_read_config32(device_t dev, unsigned where)
+static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
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