[coreboot-gerrit] Patch set updated for coreboot: 0f54563 southbridge: Don't hide pointers behind typedefs
Edward O'Callaghan (eocallaghan@alterapraxis.com)
gerrit at coreboot.org
Sun Oct 26 02:34:08 CET 2014
Edward O'Callaghan (eocallaghan at alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7169
-gerrit
commit 0f54563502154cd2f235e8aa9c92e4118d2fbbd8
Author: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Date: Thu Oct 23 02:09:00 2014 +1100
southbridge: Don't hide pointers behind typedefs
Unfortunately coreboot has to deal with ROMCC's short comings which has
lead to a little bit of confusion due to typedefs. Essentially, coreboot
defines four typedefs:
* 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode
* 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined
* 'typedef u32 pnp_devfn_t'
* 'typedef u32 pci_devfn_t'
Some early functions make use of 'device_t' over 'pci_devfn_t' and since
the C type-checker does not enforce typedefs to the same type 'u32'
these are never noticed. Fix these so that 'device_t' does not conflict
in romstage for later work. We later plan to have 'pnp_devfn_t' and
'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a
struct pointer type exclusively.
Change-Id: Id6c221cc36a2b89db7b11796d947136bac76e565
Signed-off-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
---
src/southbridge/amd/agesa/hudson/spi.c | 2 +-
src/southbridge/amd/cimx/sb700/early.c | 6 +++---
src/southbridge/amd/cimx/sb800/early.c | 2 +-
src/southbridge/amd/cimx/sb800/spi.c | 2 +-
src/southbridge/amd/sb600/early_setup.c | 14 +++++++-------
src/southbridge/amd/sb700/early_setup.c | 18 +++++++++---------
src/southbridge/broadcom/bcm5780/nic.c | 2 +-
src/southbridge/broadcom/bcm5780/pcix.c | 2 +-
src/southbridge/broadcom/bcm5785/bcm5785.c | 6 +++---
src/southbridge/broadcom/bcm5785/bcm5785.h | 2 +-
src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++-----
src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +-
src/southbridge/broadcom/bcm5785/ide.c | 4 ++--
src/southbridge/broadcom/bcm5785/lpc.c | 12 ++++++------
src/southbridge/broadcom/bcm5785/sata.c | 2 +-
src/southbridge/broadcom/bcm5785/sb_pci_main.c | 14 +++++++-------
src/southbridge/broadcom/bcm5785/usb.c | 2 +-
src/southbridge/dmp/vortex86ex/southbridge.c | 10 +++++-----
src/southbridge/intel/common/spi.c | 2 +-
src/southbridge/intel/fsp_rangeley/spi.c | 2 +-
src/southbridge/nvidia/ck804/ck804.c | 10 +++++-----
src/southbridge/nvidia/ck804/lpc.c | 18 +++++++++---------
src/southbridge/nvidia/ck804/smbus.c | 8 ++++----
src/southbridge/nvidia/mcp55/azalia.c | 2 +-
src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +-
src/southbridge/nvidia/mcp55/lpc.c | 14 +++++++-------
src/southbridge/nvidia/mcp55/mcp55.h | 2 +-
src/southbridge/nvidia/mcp55/smbus.c | 12 ++++++------
src/southbridge/sis/sis966/early_ctrl.c | 2 +-
29 files changed, 93 insertions(+), 93 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index bbf6dd3..ce22d34 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -86,7 +86,7 @@ static void execute_command(void)
void spi_init(void)
{
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
index 6dc4ff4..b606352 100644
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ b/src/southbridge/amd/cimx/sb700/early.c
@@ -34,7 +34,7 @@
*/
u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
dev = pci_locate_device_on_bus(
@@ -69,7 +69,7 @@ void sb_Poweron_Init(void)
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
@@ -83,7 +83,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
void sb7xx_51xx_disable_wideio(u8 wio_index)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
//dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c
index 40648ed..0341567 100644
--- a/src/southbridge/amd/cimx/sb800/early.c
+++ b/src/southbridge/amd/cimx/sb800/early.c
@@ -33,7 +33,7 @@
*/
u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
//dev = PCI_DEV(bus, 0x14, 0);
diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c
index f38e691..86e4f89 100644
--- a/src/southbridge/amd/cimx/sb800/spi.c
+++ b/src/southbridge/amd/cimx/sb800/spi.c
@@ -53,7 +53,7 @@ static void execute_command(void)
void spi_init()
{
- device_t dev;
+ struct device * dev;
dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c
index b6611f6..e412217 100644
--- a/src/southbridge/amd/sb600/early_setup.c
+++ b/src/southbridge/amd/sb600/early_setup.c
@@ -40,7 +40,7 @@ static u8 pmio_read(u8 reg)
/* RPR 2.1: Get SB ASIC Revision. */
static u8 get_sb600_revision(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
if (dev == PCI_DEV_INVALID) {
@@ -67,7 +67,7 @@ static void sb600_lpc_init(void)
{
u8 reg8;
u32 reg32;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
@@ -106,7 +106,7 @@ static void sb600_lpc_init(void)
/* what is its usage? */
static u32 get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -196,7 +196,7 @@ void soft_reset(void)
void sb600_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -241,7 +241,7 @@ void sb600_pci_port80(void)
void sb600_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
u32 reg32;
/* Enable LPC controller */
@@ -260,7 +260,7 @@ void sb600_lpc_port80(void)
/* sbDevicesPorInitTable */
static void sb600_devices_por_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
printk(BIOS_INFO, "sb600_devices_por_init()\n");
@@ -520,7 +520,7 @@ static void sb600_pmio_por_init(void)
*/
static void sb600_pci_cfg(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index b7a5e77..90dbfa8 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -79,7 +79,7 @@ static void sb700_acpi_init(void)
/* RPR 2.28: Get SB ASIC Revision. */
static u8 set_sb700_revision(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 rev_id, enable_14Mhz, byte;
u8 rev = 0;
@@ -136,7 +136,7 @@ void sb7xx_51xx_lpc_init(void)
{
u8 reg8;
u32 reg32;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0); /* SMBUS controller */
/* NOTE: Set BootTimerDisable, otherwise it would keep rebooting!!
@@ -195,7 +195,7 @@ void sb7xx_51xx_lpc_init(void)
void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
@@ -208,7 +208,7 @@ void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
void sb7xx_51xx_disable_wideio(u8 wio_index)
{
/* TODO: Now assume wio_index=0 */
- device_t dev;
+ pci_devfn_t dev;
u8 reg8;
dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
@@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index)
/* what is its usage? */
u32 __attribute__ ((weak)) get_sbdn(u32 bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
@@ -290,7 +290,7 @@ void __attribute__((weak)) enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
void sb7xx_51xx_pci_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
/* P2P Bridge */
dev = pci_locate_device(PCI_ID(0x1002, 0x4384), 0);
@@ -335,7 +335,7 @@ void sb7xx_51xx_pci_port80(void)
void sb7xx_51xx_lpc_port80(void)
{
u8 byte;
- device_t dev;
+ pci_devfn_t dev;
u32 reg32;
/* Enable LPC controller */
@@ -354,7 +354,7 @@ void sb7xx_51xx_lpc_port80(void)
/* sbDevicesPorInitTable */
static void sb700_devices_por_init(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100
u32 dword;
@@ -607,7 +607,7 @@ static void sb700_pmio_por_init(void)
*/
static void sb700_pci_cfg(void)
{
- device_t dev;
+ pci_devfn_t dev;
u8 byte;
/* SMBus Device, BDF:0-20-0 */
diff --git a/src/southbridge/broadcom/bcm5780/nic.c b/src/southbridge/broadcom/bcm5780/nic.c
index df59fdc..5fd56dd 100644
--- a/src/southbridge/broadcom/bcm5780/nic.c
+++ b/src/southbridge/broadcom/bcm5780/nic.c
@@ -25,7 +25,7 @@
#include <device/pci_ops.h>
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5780/pcix.c b/src/southbridge/broadcom/bcm5780/pcix.c
index 92a3547..96d0ace 100644
--- a/src/southbridge/broadcom/bcm5780/pcix.c
+++ b/src/southbridge/broadcom/bcm5780/pcix.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 1675097..822b3ba 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -24,10 +24,10 @@
#include <device/pci_ids.h>
#include "bcm5785.h"
-void bcm5785_enable(device_t dev)
+void bcm5785_enable(struct device * dev)
{
- device_t sb_pci_main_dev;
- device_t bus_dev;
+ struct device * sb_pci_main_dev;
+ struct device * bus_dev;
// unsigned index;
/* See if we are on the behind the pcix bridge */
diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.h b/src/southbridge/broadcom/bcm5785/bcm5785.h
index bc3280f..5eb2f05 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.h
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.h
@@ -24,7 +24,7 @@
#include "chip.h"
#ifndef __PRE_RAM__
-void bcm5785_enable(device_t dev);
+void bcm5785_enable(struct device * dev);
#else
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
#endif
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 9dee295..fe0fded 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -24,7 +24,7 @@
static void bcm5785_enable_lpc(void)
{
uint8_t byte;
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
@@ -43,7 +43,7 @@ static void bcm5785_enable_lpc(void)
static void bcm5785_enable_wdt_port_cf9(void)
{
- device_t dev;
+ pci_devfn_t dev;
uint32_t dword;
uint32_t dword_old;
@@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void)
unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device.
* There can only be one bcm5785 on a hypertransport chain/bus.
@@ -134,7 +134,7 @@ void soft_reset(void)
static void bcm5785_enable_msg(void)
{
- device_t dev;
+ pci_devfn_t dev;
uint32_t dword;
uint32_t dword_old;
uint8_t byte;
@@ -162,7 +162,7 @@ static void bcm5785_early_setup(void)
{
uint8_t byte;
uint32_t dword;
- device_t dev;
+ pci_devfn_t dev;
//F0
// enable device on bcm5785 at first
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 38e58f8..200da09 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -24,7 +24,7 @@
static void enable_smbus(void)
{
- device_t dev;
+ pci_devfn_t dev;
dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
if (dev == PCI_DEV_INVALID) {
diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c
index 3426a2c..948fef0 100644
--- a/src/southbridge/broadcom/bcm5785/ide.c
+++ b/src/southbridge/broadcom/bcm5785/ide.c
@@ -25,7 +25,7 @@
#include <device/pci_ops.h>
#include "bcm5785.h"
-static void bcm5785_ide_read_resources(device_t dev)
+static void bcm5785_ide_read_resources(struct device * dev)
{
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
@@ -40,7 +40,7 @@ static void ide_init(struct device *dev)
{
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5785/lpc.c b/src/southbridge/broadcom/bcm5785/lpc.c
index af79892..5cf1376 100644
--- a/src/southbridge/broadcom/bcm5785/lpc.c
+++ b/src/southbridge/broadcom/bcm5785/lpc.c
@@ -30,7 +30,7 @@
#include <arch/ioapic.h>
#include "bcm5785.h"
-static void lpc_init(device_t dev)
+static void lpc_init(struct device * dev)
{
/* Initialize the real time clock */
cmos_init(0);
@@ -39,7 +39,7 @@ static void lpc_init(device_t dev)
isa_dma_init();
}
-static void bcm5785_lpc_read_resources(device_t dev)
+static void bcm5785_lpc_read_resources(struct device * dev)
{
struct resource *res;
@@ -70,7 +70,7 @@ static void bcm5785_lpc_read_resources(device_t dev)
*
* @param dev The device whos children's resources are to be enabled.
*/
-static void bcm5785_lpc_enable_childrens_resources(device_t dev)
+static void bcm5785_lpc_enable_childrens_resources(struct device * dev)
{
struct bus *link;
uint32_t reg;
@@ -78,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config8(dev, 0x44);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device * child;
for (child = link->children; child; child = child->sibling) {
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
@@ -114,13 +114,13 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
}
-static void bcm5785_lpc_enable_resources(device_t dev)
+static void bcm5785_lpc_enable_resources(struct device * dev)
{
pci_dev_enable_resources(dev);
bcm5785_lpc_enable_childrens_resources(dev);
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5785/sata.c b/src/southbridge/broadcom/bcm5785/sata.c
index 62eab45..ddcb44c 100644
--- a/src/southbridge/broadcom/bcm5785/sata.c
+++ b/src/southbridge/broadcom/bcm5785/sata.c
@@ -73,7 +73,7 @@ static void sata_init(struct device *dev)
}
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
index 3745cef..0e42863 100644
--- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c
+++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c
@@ -33,7 +33,7 @@
#define NMI_OFF 0
-static void sb_init(device_t dev)
+static void sb_init(struct device * dev)
{
uint8_t byte;
uint8_t byte_old;
@@ -56,7 +56,7 @@ static void sb_init(device_t dev)
}
-static void bcm5785_sb_read_resources(device_t dev)
+static void bcm5785_sb_read_resources(struct device * dev)
{
struct resource *res;
@@ -76,7 +76,7 @@ static void bcm5785_sb_read_resources(device_t dev)
}
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device * dev)
{
unsigned device;
struct resource *res;
@@ -90,7 +90,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, uint8_t val)
+static int lsmbus_send_byte(struct device * dev, uint8_t val)
{
unsigned device;
struct resource *res;
@@ -104,7 +104,7 @@ static int lsmbus_send_byte(device_t dev, uint8_t val)
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, uint8_t address)
+static int lsmbus_read_byte(struct device * dev, uint8_t address)
{
unsigned device;
struct resource *res;
@@ -118,7 +118,7 @@ static int lsmbus_read_byte(device_t dev, uint8_t address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
+static int lsmbus_write_byte(struct device * dev, uint8_t address, uint8_t val)
{
unsigned device;
struct resource *res;
@@ -139,7 +139,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
.write_byte = lsmbus_write_byte,
};
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x2c,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/broadcom/bcm5785/usb.c b/src/southbridge/broadcom/bcm5785/usb.c
index cb4a498..b9c2452 100644
--- a/src/southbridge/broadcom/bcm5785/usb.c
+++ b/src/southbridge/broadcom/bcm5785/usb.c
@@ -37,7 +37,7 @@ static void usb_init(struct device *dev)
}
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void lpci_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index d4f263b..b65fd11 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -95,7 +95,7 @@ static const unsigned char irq_to_int_routing[16] = {
/* keyboard controller system flag timeout : 400 ms */
#define KBC_TIMEOUT_SYS_FLAG 400
-static u8 get_pci_dev_func(device_t dev)
+static u8 get_pci_dev_func(struct device * dev)
{
return PCI_FUNC(dev->path.pci.devfn);
}
@@ -182,7 +182,7 @@ static void pci_routing_fixup(struct device *dev)
/* Read PCI slot IRQs to see if RT1-3 is used, and enables it */
for (i = 0; i < slot_num; i++) {
unsigned int funct;
- device_t pdev;
+ struct device * pdev;
u8 irq;
/* Each slot may contain up to eight functions. */
@@ -515,7 +515,7 @@ static void fix_cmos_rtc_time(void)
}
}
-static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32 size)
+static void vortex86_sb_set_io_resv(struct device * dev, unsigned index, u32 base, u32 size)
{
struct resource *res;
res = new_resource(dev, index);
@@ -525,7 +525,7 @@ static void vortex86_sb_set_io_resv(device_t dev, unsigned index, u32 base, u32
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 flash_size)
+static void vortex86_sb_set_spi_flash_size(struct device * dev, unsigned index, u32 flash_size)
{
/* SPI flash is in topmost of 4G memory space */
struct resource *res;
@@ -536,7 +536,7 @@ static void vortex86_sb_set_spi_flash_size(device_t dev, unsigned index, u32 fla
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
-static void vortex86_sb_read_resources(device_t dev)
+static void vortex86_sb_read_resources(struct device * dev)
{
u32 flash_size = 8 * 1024 * 1024;
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 2ea9a24..e5783e7 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -322,7 +322,7 @@ void spi_init(void)
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- device_t dev;
+ struct device * dev;
ich9_spi_regs *ich9_spi;
uint16_t hsfs;
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index 6df99fd..c4e8a1c 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -370,7 +370,7 @@ void spi_init(void)
{
int ich_version = 0;
uint8_t bios_cntl;
- device_t dev;
+ struct device * dev;
uint32_t ids;
uint16_t vendor_id, device_id;
diff --git a/src/southbridge/nvidia/ck804/ck804.c b/src/southbridge/nvidia/ck804/ck804.c
index 353a4bd..a285938 100644
--- a/src/southbridge/nvidia/ck804/ck804.c
+++ b/src/southbridge/nvidia/ck804/ck804.c
@@ -28,9 +28,9 @@
static u32 final_reg;
-static device_t find_lpc_dev(device_t dev, unsigned devfn)
+static struct device * find_lpc_dev(struct device * dev, unsigned devfn)
{
- device_t lpc_dev;
+ struct device * lpc_dev;
lpc_dev = dev_find_slot(dev->bus->secondary, devfn);
if (!lpc_dev)
@@ -57,9 +57,9 @@ static device_t find_lpc_dev(device_t dev, unsigned devfn)
return lpc_dev;
}
-void ck804_enable(device_t dev)
+void ck804_enable(struct device * dev)
{
- device_t lpc_dev;
+ struct device * lpc_dev;
unsigned index = 0, index2 = 0, deviceid, vendorid, devfn;
u32 reg_old, reg;
u8 byte;
@@ -188,7 +188,7 @@ void ck804_enable(device_t dev)
}
}
-static void ck804_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void ck804_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
pci_write_config32(dev, 0x40,
((device & 0xffff) << 16) | (vendor & 0xffff));
diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c
index 9b6049c..a48401f 100644
--- a/src/southbridge/nvidia/ck804/lpc.c
+++ b/src/southbridge/nvidia/ck804/lpc.c
@@ -52,7 +52,7 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-static void lpc_common_init(device_t dev)
+static void lpc_common_init(struct device * dev)
{
u32 dword;
struct resource *res;
@@ -69,12 +69,12 @@ static void lpc_common_init(device_t dev)
#endif
}
-static void lpc_slave_init(device_t dev)
+static void lpc_slave_init(struct device * dev)
{
lpc_common_init(dev);
}
-static void rom_dummy_write(device_t dev)
+static void rom_dummy_write(struct device * dev)
{
u8 old, new;
u8 *p;
@@ -104,7 +104,7 @@ static void rom_dummy_write(device_t dev)
unsigned pm_base = 0;
-static void lpc_init(device_t dev)
+static void lpc_init(struct device * dev)
{
u8 byte, byte_old;
int on, nmi_option;
@@ -170,7 +170,7 @@ static void lpc_init(device_t dev)
rom_dummy_write(dev);
}
-static void ck804_lpc_read_resources(device_t dev)
+static void ck804_lpc_read_resources(struct device * dev)
{
struct resource *res;
unsigned long index;
@@ -215,7 +215,7 @@ static void ck804_lpc_read_resources(device_t dev)
}
}
-static void ck804_lpc_set_resources(device_t dev)
+static void ck804_lpc_set_resources(struct device * dev)
{
u8 byte;
struct resource *res;
@@ -251,7 +251,7 @@ static void ck804_lpc_set_resources(device_t dev)
* This function is called by the global enable_resources() indirectly via the
* device_operation::enable_resources() method of devices.
*/
-static void ck804_lpc_enable_childrens_resources(device_t dev)
+static void ck804_lpc_enable_childrens_resources(struct device * dev)
{
struct bus *link;
u32 reg, reg_var[4];
@@ -260,7 +260,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device * child;
for (child = link->children; child; child = child->sibling) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
@@ -307,7 +307,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
}
-static void ck804_lpc_enable_resources(device_t dev)
+static void ck804_lpc_enable_resources(struct device * dev)
{
pci_dev_enable_resources(dev);
ck804_lpc_enable_childrens_resources(dev);
diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c
index dd6a5f4..62967bf 100644
--- a/src/southbridge/nvidia/ck804/smbus.c
+++ b/src/southbridge/nvidia/ck804/smbus.c
@@ -28,7 +28,7 @@
#include "ck804.h"
#include "smbus.h"
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device * dev)
{
unsigned device;
struct resource *res;
@@ -42,7 +42,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device * dev, u8 val)
{
unsigned device;
struct resource *res;
@@ -56,7 +56,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device * dev, u8 address)
{
unsigned device;
struct resource *res;
@@ -70,7 +70,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device * dev, u8 address, u8 val)
{
unsigned device;
struct resource *res;
diff --git a/src/southbridge/nvidia/mcp55/azalia.c b/src/southbridge/nvidia/mcp55/azalia.c
index 67433d3..954e305 100644
--- a/src/southbridge/nvidia/mcp55/azalia.c
+++ b/src/southbridge/nvidia/mcp55/azalia.c
@@ -254,7 +254,7 @@ static void azalia_init(struct device *dev)
}
}
-static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+static void azalia_set_subsystem(struct device * dev, unsigned vendor, unsigned device)
{
if (!vendor || !device) {
pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c
index 92f9d03..865c023 100644
--- a/src/southbridge/nvidia/mcp55/early_ctrl.c
+++ b/src/southbridge/nvidia/mcp55/early_ctrl.c
@@ -24,7 +24,7 @@
static unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c
index 11c2c4f..ebf2a01 100644
--- a/src/southbridge/nvidia/mcp55/lpc.c
+++ b/src/southbridge/nvidia/mcp55/lpc.c
@@ -57,7 +57,7 @@
#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
-static void lpc_common_init(device_t dev, int master)
+static void lpc_common_init(struct device * dev, int master)
{
u8 byte;
u32 ioapic_base;
@@ -74,7 +74,7 @@ static void lpc_common_init(device_t dev, int master)
clear_ioapic(ioapic_base);
}
-static void lpc_slave_init(device_t dev)
+static void lpc_slave_init(struct device * dev)
{
lpc_common_init(dev, 0);
}
@@ -88,7 +88,7 @@ static void enable_hpet(struct device *dev)
printk(BIOS_DEBUG, "enabling HPET @0x%lx\n", hpet_address);
}
-static void lpc_init(device_t dev)
+static void lpc_init(struct device * dev)
{
u8 byte, byte_old;
int on, nmi_option;
@@ -161,7 +161,7 @@ static void lpc_init(device_t dev)
enable_hpet(dev);
}
-static void mcp55_lpc_read_resources(device_t dev)
+static void mcp55_lpc_read_resources(struct device * dev)
{
struct resource *res;
@@ -193,7 +193,7 @@ static void mcp55_lpc_read_resources(device_t dev)
*
* @param dev The device whose children's resources are to be enabled.
*/
-static void mcp55_lpc_enable_childrens_resources(device_t dev)
+static void mcp55_lpc_enable_childrens_resources(struct device * dev)
{
u32 reg, reg_var[4];
int i, var_num = 0;
@@ -202,7 +202,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
reg = pci_read_config32(dev, 0xa0);
for (link = dev->link_list; link; link = link->next) {
- device_t child;
+ struct device * child;
for (child = link->children; child; child = child->sibling) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
@@ -250,7 +250,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
pci_write_config32(dev, 0xa8 + i * 4, reg_var[i]);
}
-static void mcp55_lpc_enable_resources(device_t dev)
+static void mcp55_lpc_enable_resources(struct device * dev)
{
pci_dev_enable_resources(dev);
mcp55_lpc_enable_childrens_resources(dev);
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 4fb3391..20b33b4 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -30,7 +30,7 @@
#ifndef __PRE_RAM__
#include "chip.h"
-void mcp55_enable(device_t dev);
+void mcp55_enable(struct device * dev);
extern struct pci_operations mcp55_pci_ops;
#else
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c
index 3e0b87e..e28a896 100644
--- a/src/southbridge/nvidia/mcp55/smbus.c
+++ b/src/southbridge/nvidia/mcp55/smbus.c
@@ -31,7 +31,7 @@
#include "mcp55.h"
#include "smbus.h"
-static int lsmbus_recv_byte(device_t dev)
+static int lsmbus_recv_byte(struct device * dev)
{
unsigned device;
struct resource *res;
@@ -45,7 +45,7 @@ static int lsmbus_recv_byte(device_t dev)
return do_smbus_recv_byte(res->base, device);
}
-static int lsmbus_send_byte(device_t dev, u8 val)
+static int lsmbus_send_byte(struct device * dev, u8 val)
{
unsigned device;
struct resource *res;
@@ -59,7 +59,7 @@ static int lsmbus_send_byte(device_t dev, u8 val)
return do_smbus_send_byte(res->base, device, val);
}
-static int lsmbus_read_byte(device_t dev, u8 address)
+static int lsmbus_read_byte(struct device * dev, u8 address)
{
unsigned device;
struct resource *res;
@@ -73,7 +73,7 @@ static int lsmbus_read_byte(device_t dev, u8 address)
return do_smbus_read_byte(res->base, device, address);
}
-static int lsmbus_write_byte(device_t dev, u8 address, u8 val)
+static int lsmbus_write_byte(struct device * dev, u8 address, u8 val)
{
unsigned device;
struct resource *res;
@@ -97,7 +97,7 @@ static struct smbus_bus_operations lops_smbus_bus = {
unsigned pm_base;
#endif
-static void mcp55_sm_read_resources(device_t dev)
+static void mcp55_sm_read_resources(struct device * dev)
{
unsigned long index;
@@ -110,7 +110,7 @@ static void mcp55_sm_read_resources(device_t dev)
compact_resources(dev);
}
-static void mcp55_sm_init(device_t dev)
+static void mcp55_sm_init(struct device * dev)
{
#if CONFIG_HAVE_ACPI_TABLES
struct resource *res;
diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c
index 3695023..4b3a228 100644
--- a/src/southbridge/sis/sis966/early_ctrl.c
+++ b/src/southbridge/sis/sis966/early_ctrl.c
@@ -23,7 +23,7 @@
static unsigned get_sbdn(unsigned bus)
{
- device_t dev;
+ pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(
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