[coreboot-gerrit] New patch to review for coreboot: deb3ab5 baytrail: gfx: Don't configure hotplug + backlight registers
Marc Jones (marc.jones@se-eng.com)
gerrit at coreboot.org
Tue Oct 28 00:05:58 CET 2014
Marc Jones (marc.jones at se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7217
-gerrit
commit deb3ab5c8e092baf466e519e5dd977720d4df160
Author: Shawn Nematbakhsh <shawnn at chromium.org>
Date: Wed Apr 9 12:41:22 2014 -0700
baytrail: gfx: Don't configure hotplug + backlight registers
- The hotplug register doesn't work in the way we describe. Just leave
it at default.
- The backlight registers will be configured by the OS driver.
BUG=chrome-os-partner:27304
TEST=Manual on Rambi. Boot system in both dev and normal mode, verify
that display comes up. Also verify that display functions after warm
reboot and suspend / resume.
BRANCH=rambi+squawks
Change-Id: I5559c131f41c4a14e64e5cec66e18d3a4a46092c
Signed-off-by: Shawn Nematbakhsh <shawnn at chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193830
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
(cherry picked from commit 3f287cc31e41fabef755c37361e2e65ca413c88c)
Signed-off-by: Marc Jones <marc.jones at se-eng.com>
---
src/soc/intel/baytrail/gfx.c | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 4ed08c9..9d4768f 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -296,9 +296,6 @@ static void gfx_panel_setup(device_t dev)
/* CONTROL */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* HOTPLUG */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL),
- 0x1 | (config->gpu_pipea_hotplug << 2)),
/* POWER ON */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS),
(config->gpu_pipea_port_select << 30 |
@@ -311,21 +308,12 @@ static void gfx_panel_setup(device_t dev)
/* DIVISOR */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR),
~0x1f, config->gpu_pipea_power_cycle_delay),
- /* BACKLIGHT */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL),
- (config->gpu_pipea_backlight_pwm << 16) |
- (config->gpu_pipea_backlight_pwm >> 1)),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2),
- BACKLIGHT_ENABLE),
REG_SCRIPT_END
};
struct reg_script gfx_pipeb_init[] = {
/* CONTROL */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL),
PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD),
- /* HOTPLUG */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL),
- 0x1 | (config->gpu_pipeb_hotplug << 2)),
/* POWER ON */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS),
(config->gpu_pipeb_port_select << 30 |
@@ -338,12 +326,6 @@ static void gfx_panel_setup(device_t dev)
/* DIVISOR */
REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR),
~0x1f, config->gpu_pipeb_power_cycle_delay),
- /* BACKLIGHT */
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL),
- (config->gpu_pipeb_backlight_pwm << 16) |
- (config->gpu_pipeb_backlight_pwm >> 1)),
- REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2),
- BACKLIGHT_ENABLE),
REG_SCRIPT_END
};
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