[coreboot-gerrit] Patch merged into coreboot/master: a2c4f9e imgtec/pistachio: DDR row/bank/column mapping
gerrit at coreboot.org
gerrit at coreboot.org
Wed Apr 22 08:59:47 CEST 2015
the following patch was just integrated into master:
commit a2c4f9ee9fbedfe540145350b121f5ffb9ce0b67
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Mon Mar 30 11:59:10 2015 +0100
imgtec/pistachio: DDR row/bank/column mapping
The DRAM configuration register, apart from holding the
device density and width also has a rudimentary address
mapping scheme. Currently this is set to the default
Bank/Row/Column. This means that the memory is segmented
into 8 chunks, each with a page detector. If all the
activity is in one section of memory then the other 7
page detectors could be idle.
Changing this to Row/Bank/Column would concatenate the
page detectors meaning that all 8 could be used by a
single initiator. This may not gain anything in a
synthetic bandwidth test but could yield extra performance
in a real world application or benchmark.
BRANCH=none
BUG=chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly; all access to DDR works properly in
Coreboot ramstage, Depthcharge and Linux;
no performance tests were ran so far.
Change-Id: I22d86bf3b679ed63884d7436d9d7bbaf1726f640
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: e852ed42afcdc2062a0037144bab723227cb1f1f
Original-Change-Id: If90b0cf5ce86db5e3d6d362873d22d4269e3a49f
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/264340
Original-Reviewed-by: James Hartley <james.hartley at imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Reviewed-on: http://review.coreboot.org/9916
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
See http://review.coreboot.org/9916 for details.
-gerrit
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