[coreboot-gerrit] Patch merged into coreboot/master: 5d997f9 imgtec/pistachio: DDR reads return to controller with no bubbles
gerrit at coreboot.org
gerrit at coreboot.org
Wed Apr 22 09:00:07 CEST 2015
the following patch was just integrated into master:
commit 5d997f9459e95c52ed70f98ab0db2320cf8d6238
Author: Ionela Voinescu <ionela.voinescu at imgtec.com>
Date: Mon Mar 30 12:00:35 2015 +0100
imgtec/pistachio: DDR reads return to controller with no bubbles
When the PHY is compiled to run in HDR(half data rate),
then either NOBUB or FXDAT must be set to 1 in the DDR
system general configuration register. NOBUB specifies
that reads should be returned to the controller with
no bubbles and this is felt preferable to the fixed
latency option (FXDAT). Both of them inrease read
latency.
BRANCH=none
BUG=chrome-os-partner:37087
TEST=tested on Pistachio bring up board -> DDR initialized
properly and ramstage executed correctly
Change-Id: Iee530ba5bb0acc889fba447dc2ee5cb965ba6926
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: e7944b4af45d9504098f8b4af44d0f5abafea42c
Original-Change-Id: I9ced76bd670fc4efa7441d57e15f97871b046ae9
Original-Signed-off-by: Ionela Voinescu <ionela.voinescu at imgtec.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/264341
Original-Reviewed-by: James Hartley <james.hartley at imgtec.com>
Original-Reviewed-by: David Hendricks <dhendrix at chromium.org>
Reviewed-on: http://review.coreboot.org/9917
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer at coreboot.org>
See http://review.coreboot.org/9917 for details.
-gerrit
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