[coreboot-gerrit] New patch to review for coreboot: skylake: clear write-1-to-clear fields in power regs

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11186

-gerrit

commit 12d7149cc793f3800723d990682cfe26d9db9fcb
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Tue Aug 4 21:04:02 2015 -0500

    skylake: clear write-1-to-clear fields in power regs
    
    Explicitly clear all write-1-to-clear fields in the
    appropriate power state registers. That way stale
    state isn't left around from boot to boot. The
    MMIO PMC registers are always added such that the
    resource can be accessed from reg_script. It doesn't
    hurt to add the resource, and it's actually more
    informative by attaching the actual resources
    owned by the device.
    
    BUG=chrome-os-partner:43625
    BRANCH=None
    TEST=Built and boot glados. Did global reset. Noticed bits
         set. Did normal reset and saw those same bits no longer set.
    
    Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e
    Original-Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Original-Reviewed-on: https://chromium-review.googlesource.com/290339
    
    Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 src/soc/intel/skylake/pmc.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c
index a97f751..2c794ca 100644
--- a/src/soc/intel/skylake/pmc.c
+++ b/src/soc/intel/skylake/pmc.c
@@ -51,23 +51,25 @@ static const struct reg_script pch_pmc_misc_init_script[] = {
 	REG_SCRIPT_END
 };
 
+static const struct reg_script pmc_write1_to_clear_script[] = {
+	REG_PCI_OR32(GEN_PMCON_A, 0),
+	REG_PCI_OR32(GEN_PMCON_B, 0),
+	REG_PCI_OR32(GEN_PMCON_B, 0),
+	REG_RES_OR32(PWRMBASE, GBLRST_CAUSE0, 0),
+	REG_RES_OR32(PWRMBASE, GBLRST_CAUSE1, 0),
+	REG_SCRIPT_END
+};
+
 static void pch_pmc_add_mmio_resources(device_t dev)
 {
 	struct resource *res;
-	const u32 default_decode_base = PCH_PCR_BASE_ADDRESS;
 
-	/*
-	 * Till PCI enumeration happens we need to allocate the PMC base
-	 * statically. Above the PCR base.
-	 */
-	if (PCH_PWRM_BASE_ADDRESS < default_decode_base) {
-		res = new_resource(dev, PWRMBASE);
-		res->base = PCH_PWRM_BASE_ADDRESS;
-		/* 64KB PMC size */
-		res->size = 0x10000;
-		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
-				IORESOURCE_FIXED | IORESOURCE_RESERVE;
-	}
+	/* Memory-mmapped I/O registers. */
+	res = new_resource(dev, PWRMBASE);
+	res->base = PCH_PWRM_BASE_ADDRESS;
+	res->size = PCH_PWRM_BASE_SIZE;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
+			IORESOURCE_FIXED | IORESOURCE_RESERVE;
 }
 
 static void pch_pmc_add_io_resource(device_t dev, u16 base, u16 size, int index)
@@ -248,6 +250,9 @@ static void pmc_init(struct device *dev)
 	config_deep_s3(config->deep_s3_enable);
 	config_deep_s5(config->deep_s5_enable);
 	config_deep_sx(config->deep_sx_config);
+
+	/* Clear registers that contain write-1-to-clear bits. */
+	reg_script_run_on_dev(dev, pmc_write1_to_clear_script);
 }
 
 static struct device_operations device_ops = {